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...s, I would like to hear them. > > Andy, Thank you for writing such a detailed response. > If you annotate loads with their expected latency, the upcoming > MachineScheduler will be able to use the information. In the short > term (next couple months), you're free to hack the SDScheduler as > well. Alright, sounds good. If I add metadata to the load, can I get to it thought the Value * in the associated MachineMemOperand object? > > Although the scheduler can use the information, I don't think it can > do much good with it scheduling for mainstream targets. It w...

...r instructions that need FuncU). It's the list scheduler itself that "enforces" operand latency. MI scheduler allows you to use a new machine model that's simpler for most people who don't need the precision of Itineraries. Maybe not important in your case. More importantly, SDScheduler is take-it-as-is, and will go away entirely after 3.3. Whereas MI scheduler can be fixed and improved. Now would be a good time to try switching over and start filing bugs. PPC is an example of using MI scheduler out-of-box. Hexagon is an example of customizing it at a high level. You could start o...

...er > itself that "enforces" operand latency. > Ah okay, thank you. > MI scheduler allows you to use a new machine model that's simpler for > most people who don't need the precision of Itineraries. Maybe not > important in your case. > > More importantly, SDScheduler is take-it-as-is, and will go away > entirely after 3.3. Whereas MI scheduler can be fixed and improved. > Now would be a good time to try switching over and start filing bugs. > PPC is an example of using MI scheduler out-of-box. Hexagon is an > example of customizing it at a high...

...then account for the prefetches). > > If anyone has thoughts on these ideas, I would like to hear them. If you annotate loads with their expected latency, the upcoming MachineScheduler will be able to use the information. In the short term (next couple months), you're free to hack the SDScheduler as well. Although the scheduler can use the information, I don't think it can do much good with it scheduling for mainstream targets. It would be more interesting scheduling for an in-order machine without a hardware prefetch unit. An acyclic instruction scheduler can schedule for L1 and L2 l...

I have an instruction that takes no operands, and produces two results, in two consecutive cycles. I tried both of the following to my Schedule.td file: InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, [FuncU]>], [1, 2]>, From what I can see in examples, these say that the first

Hello, I am interested in writing an analysis pass that looks at the stride used for loads in a loop and passes that information down so that it can be used by the instruction scheduler. The reason is that if the load stride is greater than the cache line size, then I would expect the load to always miss the cache, and, as a result, the scheduler should use a much larger effective latency when

...d resource usage with register pressure avoidance. 5. Improved heuristics. For example, we can precompute register lineages and use that information to avoid high register pressure situations. The overarching goal of the standard scheduling algorithm is to handle the most important cases that the SDScheduler and PostRAScheduler handle today without unnecessarily shuffling instructions. This should result in more debugable generated code with more stable performance. The goal of the scheduler framework is to support the standard scheduler while providing a place for targets to introduce a custom schedul...

Hey Everyone, I'd like to begin a project to rework the scheduler to address some problems we've discovered on this end. The goal is to get a more configurable/flexible scheduler while simplifying maintenance by separating policy from implementation to get independent and interchangeable parts. This is going to be challenging because we are still stuck on LLVM 2.9. We will be upgrading