search for: sdpatternoperator

Hi, I implemented a pattern matching of the dot product for arm64 and it seemed to work well for the basic case, i.e., class mulB<SDPatternOperator ldop> : PatFrag<(ops node:$Rn, node:$Rm, node:$offset), (mul (ldop (add node:$Rn, node:$offset)), (ldop (add node:$Rm, node:$offset)))>; class mulBz<SDPatternOperator ldop> : PatFrag<(ops node:$Rn, node:$Rm), (mul (ldop node:$Rn), (ldop node:...

...m X86InstrFMA.td in the below example. Consider FMA3 pattern (simplified). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, RegisterClass RC, ValueType OpVT, PatFrag mem_frag, SDPatternOperator OpNode = null_frag> { def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set RC:$dst,...

...an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addrsrc); string AsmString = !strconcat("mov...

...f Mips MSA - see https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look for "def ST_D", etc. Note however that my vector unit has a separate memory space. This is why I defined the vector store like: class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst...

...example. Consider FMA3 pattern > (simplified). > > let Constraints = "$src1 = $dst" in { > multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, > RegisterClass RC, ValueType OpVT, PatFrag mem_frag, > SDPatternOperator OpNode = null_frag> { > > def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), > (ins RC:$src1, RC:$src2, RC:$src3), > !strconcat(OpcodeStr, > "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), >...

...store i32 %add, i32* %a, align 4 ret void } On x86, this gets turned into: addl $3, (%rdi) retq From X86InstrArithmetic.td: // BinOpMI8_RMW - Instructions like "add [mem], imm8". class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo, SDPatternOperator opnode, Format f> : BinOpMI8<mnemonic, typeinfo, f, [(store (opnode (load addr:$dst), typeinfo.Imm8Operator:$src), addr:$dst), (implicit EFLAGS)]>; -Eli -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Cent...

...e of Mips MSA - see https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look for "def ST_D", etc. Note however that my vector unit has a separate memory space. This is why I defined the vector store like: class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst...

...ZExt16x : ImmLeaf<i16, [{ return isUInt<16>(Imm); }]>; >> >> defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, >> GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; >> >> multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, >> RegisterClass srcAReg, RegisterClass srcBReg, >> RegisterClass dstReg, ValueType srcAType, ValueType >> srcBType, ValueType dstType, >> Operand ImmOd, ImmLeaf imm_type> >> { >> .... >> def IMM_MEM_MEM...

...confused and lost. Thanks for bearing with me. Here's my current definition: def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; class StackAddress : CodePatPred<[{ return cast<MemSDNode>(N)->getAddressSpace() == 1; }]>; class StoreFrag<SDPatternOperator op> : PatFrag < (ops node:$value, node:$ptr), (op node:$value, node:$ptr) >; class StackStore <SDPatternOperator op> : StoreFrag <op>, StackAddress; def store_stack : StackStore<store>; def StoreStackF : InstRI<2, (outs), (ins IntRegs:$reg, i32imm:$i),...

On Mon, Jun 24, 2019 at 4:08 PM Tim Northover <t.p.northover at gmail.com> wrote: > On Mon, 24 Jun 2019 at 12:16, Gleb Popov via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > 1. Where does it come from? Can I do anything to make it not appear? > > It comes from something like: > > %ptr = alloca i8 > %var = alloca i8* > store i8* %ptr, i8**

...return isInt<16>(Imm); }]>; def immZExt16x : ImmLeaf<i16, [{ return isUInt<16>(Imm); }]>; defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass srcBReg, RegisterClass dstReg, ValueType srcAType, ValueType srcBType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { .... def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx,...

...; > (simplified). > > > > let Constraints = "$src1 = $dst" in { > > multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand > x86memop, > > RegisterClass RC, ValueType OpVT, PatFrag mem_frag, > > SDPatternOperator OpNode = null_frag> { > > > > def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), > > (ins RC:$src1, RC:$src2, RC:$src3), > > !strconcat(OpcodeStr, > > "\t{$src3, $src2, $dst|$dst, $src2, &gt...

...ed from > Mips' MSA SIMD > extensions.) > Could you please tell me what's the right way to do it? > > > Here, the load class has $addrsrc which is a relative address with base a > certain > register and offset: > class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, > ValueType TyNode, RegisterOperand ROWD, > Operand MemOpnd = mem_msa, > ComplexPattern Addr = addrimm10, > InstrItinClass itin = NoItinerary> { > dag OutOperandList = (outs ROWD:$wd); > dag InOperandList = (ins MemOpnd:$addrsrc); > strin...

> On Jun 15, 2015, at 7:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > To be more specific: > > We have some operators that we are currently implementing as intrinsics, for example things like: abs, min, max, etc..... > > for some code: > > int a; > > int food() > { > return abs(a); > } > > the corresponding operator should

Thanks for your reply. We are propagating sign info to tablegen currently using BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm. I imagine (I have not looked) they are printed according to instruction in AsmPrinter.cpp (pure speculation). I'm still confused as to why 0x7FFF is ok to match 16 bit int but not 0x8000? Thanks. On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at

Here is the instruction in question: multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass dstReg, ValueType srcAType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, [(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>; def...

...d registers for the operands. On Tue, Aug 25, 2015 at 1:18 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterClass dstReg, ValueType srcAType, > ValueType dstType, Operand ImmOd, ImmLeaf imm_type> > { > def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, > [(set dstReg:$dstD, (OpNode...

...On Tue, Aug 25, 2015 at 1:18 PM, Quentin Colombet <qcolombet at apple.com> > wrote: > >> >> On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >> >> Here is the instruction in question: >> >> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >> srcAReg, >> RegisterClass dstReg, ValueType srcAType, >> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >> { >> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >> [(s...

Hi All, I am new to llvm backend. I am trying out few examples to understand backend codegen. I have ported llvm LEG @ https://github.com/frasercrmck/llvm-leg to llvm 3.9 successfully. Currently, the LEG instructions are RISC load-store type instruction. I want to generate some instructions for register indirect mode, like following: IR: @a = local_unnamed_addr global i32 0, align 4 @b =

...Quentin Colombet <qcolombet at apple.com> >> wrote: >> >>> >>> On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >>> >>> Here is the instruction in question: >>> >>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>> srcAReg, >>> RegisterClass dstReg, ValueType srcAType, >>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>> { >>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>>...