search for: sdnpcommut

.../X86SelLowering.h: add a sdnode max_qb, In /lib/Target/X86/X86SelLowering.cpp: case X86ISD::max_qb: return "X86ISD::max_qb"; In /lib/Target/X86/X86InstrInfo.td: def X86max_qb_flag : SDNode<"X86ISD::max_qb", SDTBinaryArithWithFlags, [SDNPCommutative]>; In /lib/Target/X86/X86InstrArithmetic.td: def max_qb : I<0xff,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2|$src1,$src2, $dst}", [(set GR32:$dst,EFLAGS,(X86max_qb_flag GR32:$src1, GR32:$src2))]>, Sched&l...

...ome. >> > > Are you marking add as commutable? Are you making mov as a copy > instruction? > How do I mark them? For the commutative property, I observed this definition: def add : SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; ... and assumed it was sufficient, since I saw no other targets making special arrangements. I see no obvious (to me, anyway 8^) "copy instruction" property. The insn in question is generated by copyRegToReg(), and satisfies the isMoveInstr() predicate....

...;0>, SDTCisFlag<1>, SDTCisSameAs<2, 0>, SDTCisSameAs<3, 0>]>; def Z80add_flag : SDNode<"Z80ISD::ADD", SDTBinOpRF, [SDNPCommutative]>; The unary instruction builds fine, which can be checked by commenting out the generation of the binary instruction in the last line of the attached Z80InstrInfo.td. The log in Github indicates that this section was present for over a year, so I assume that it did work at some time...

...Lowering.h: max_qb, 4.In llvm/lib/Target/X86/X86IntrinsicsInfo.h:(IntrinsicsWithoutChain) X86_INTRINSIC_DATA(max_qb, INTR_TYPE_2OP, X86ISD::max_qb, 0), 5.In llvm/lib/Target/X86/X86InstrInfo.td: def X86max_qb : SDNode<"X86ISD::max_qb", SDTBinaryArithWithFlags, [SDNPCommutative]>; 6.In X86InstrArithmetic.td: let Defs = [EFLAGS] in { let Constraints = "$src1 = $dst" in { let isCommutable = 1 in { def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb{w}\t {$dst, $src1,$src2|$dst, $src2,$...

...Lowering.h: max_qb, 4.In llvm/lib/Target/X86/X86IntrinsicsInfo.h:(IntrinsicsWithoutChain) X86_INTRINSIC_DATA(max_qb, INTR_TYPE_2OP, X86ISD::max_qb, 0), 5.In llvm/lib/Target/X86/X86InstrInfo.td: def X86max_qb : SDNode<"X86ISD::max_qb", SDTBinaryArithWithFlags, [SDNPCommutative]>; 6.In X86InstrArithmetic.td: let Defs = [EFLAGS] in { let Constraints = "$src1 = $dst" in { let isCommutable = 1 in { def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb{w}\t {$dst, $src1,$src2|$dst, $src2,$...

On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: > I have my new port limping enough to compile a very basic function: > > int > foo (int a, int b, int c, int d) > { > return a + b - c + d; > } > > clang-cc -O2 yields: > > define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { > entry: > %add = add i32 %b, %a ; <i32> [#uses=1]

...Are you marking add as commutable? Are you making mov as a copy >> instruction? >> > > How do I mark them? For the commutative property, I observed this > definition: > > def add : SDNode<"ISD::ADD" , SDTIntBinOp , > [SDNPCommutative, SDNPAssociative]>; Yes, the "target-independent" ISD::ADD node is commutative. But it doesn't mean the target specific instruction it is selected to has to be commutative. > > ... and assumed it was sufficient, since I saw no other targets making > special arra...

I have my new port limping enough to compile a very basic function: int foo (int a, int b, int c, int d) { return a + b - c + d; } clang-cc -O2 yields: define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { entry: %add = add i32 %b, %a ; <i32> [#uses=1] %sub = sub i32 %add, %c ; <i32> [#uses=1] %add4 = add i32 %sub, %d ; <i32>

...PUISD::BITALIGN", AMDGPUDTIntTernaryOp>; > + > +// out = a - floor(a) > +def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>; > + > +// out = max(a, b) a and b are floats > +def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp, > + [SDNPCommutative, SDNPAssociative] > +>; > + > +// out = max(a, b) a and b are signed ints > +def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp, > + [SDNPCommutative, SDNPAssociative] > +>; > + > +// out = max(a, b) a and b are unsigned ints > +def AMDGPUumax...

...ib/Target/R600/AMDGPUInstrInfo.td b/lib/Target/R600/AMDGPUInstrInfo.td > index 3d70791..1600c4a 100644 > --- a/lib/Target/R600/AMDGPUInstrInfo.td > +++ b/lib/Target/R600/AMDGPUInstrInfo.td > @@ -91,6 +91,12 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp, > [SDNPCommutative, SDNPAssociative] > >; > > +// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0 > +def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>; > + > +// out = (src1 > src0) ? 1 : 0 > +def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTInt...