Displaying 7 results from an estimated 7 matches for "sdnpassoci".
2009 Apr 16
3
[LLVMdev] Help me improve two-address code
...>
> Are you marking add as commutable? Are you making mov as a copy
> instruction?
>
How do I mark them? For the commutative property, I observed this
definition:
def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
[SDNPCommutative, SDNPAssociative]>;
... and assumed it was sufficient, since I saw no other targets making
special arrangements.
I see no obvious (to me, anyway 8^) "copy instruction" property. The
insn in question is generated by copyRegToReg(), and satisfies the
isMoveInstr() predicate.
G
2009 Apr 16
0
[LLVMdev] Help me improve two-address code
On Apr 16, 2009, at 3:17 PM, Greg McGary wrote:
> I have my new port limping enough to compile a very basic function:
>
> int
> foo (int a, int b, int c, int d)
> {
> return a + b - c + d;
> }
>
> clang-cc -O2 yields:
>
> define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
> entry:
> %add = add i32 %b, %a ; <i32> [#uses=1]
2009 Apr 17
0
[LLVMdev] Help me improve two-address code
...dd as commutable? Are you making mov as a copy
>> instruction?
>>
>
> How do I mark them? For the commutative property, I observed this
> definition:
>
> def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
> [SDNPCommutative, SDNPAssociative]>;
Yes, the "target-independent" ISD::ADD node is commutative. But it
doesn't mean the target specific instruction it is selected to has to
be commutative.
>
> ... and assumed it was sufficient, since I saw no other targets making
> special arrangements.
In X86...
2011 Dec 02
0
[LLVMdev] Error: Type constraint application shouldn't fail!
Hi list,
I'm trying to match a particular pattern into the SDag which looks like
this:
// non-commutative multiplication
def ncmul : SDNode<"ISD::MUL" , SDTIntBinOp,
[SDNPAssociative]>;
def mula_pat : PatFrag<(ops node:$a, node:$b),
(add
(ncmul
(sext (i16 (extractelt node:$a, (i32
0)))),
(sext (i16 (extractelt node:$b, (i...
2009 Apr 16
2
[LLVMdev] Help me improve two-address code
I have my new port limping enough to compile a very basic function:
int
foo (int a, int b, int c, int d)
{
return a + b - c + d;
}
clang-cc -O2 yields:
define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry:
%add = add i32 %b, %a ; <i32> [#uses=1]
%sub = sub i32 %add, %c ; <i32> [#uses=1]
%add4 = add i32 %sub, %d ; <i32>
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...uot;, AMDGPUDTIntTernaryOp>;
> +
> +// out = a - floor(a)
> +def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
> +
> +// out = max(a, b) a and b are floats
> +def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
> + [SDNPCommutative, SDNPAssociative]
> +>;
> +
> +// out = max(a, b) a and b are signed ints
> +def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
> + [SDNPCommutative, SDNPAssociative]
> +>;
> +
> +// out = max(a, b) a and b are unsigned ints
> +def AMDGPUumax : SDNode<&quo...
2014 Oct 03
2
[LLVMdev] Weird problems with cos (was Re: [PATCH v3 2/3] R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO)
...DGPUInstrInfo.td b/lib/Target/R600/AMDGPUInstrInfo.td
> index 3d70791..1600c4a 100644
> --- a/lib/Target/R600/AMDGPUInstrInfo.td
> +++ b/lib/Target/R600/AMDGPUInstrInfo.td
> @@ -91,6 +91,12 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
> [SDNPCommutative, SDNPAssociative]
> >;
>
> +// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
> +def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
> +
> +// out = (src1 > src0) ? 1 : 0
> +def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
&g...