search for: sdivrem

I wrote the following bit of code static APInt FloorOfQuotient(APInt a, APInt b) { unsigned bits = a.getBitWidth(); APInt q(bits, 1), r(bits, 1); APInt::sdivrem(a, b, q, r); * errs() << "sdivrem(" << a << ", " << b << ") = (" << q << ", " << r << ")\n"; * if (r == 0) return q; else { if ((a.sgt(0) && b.sgt(0)) || (a.slt(0) &&a...

OK, the code for sdivrem in APInt.h is wrong. Here's what's written: static void sdivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient, APInt &Remainder) { if (LHS.isNegative()) { if (RHS.isNegative()) APInt::udivrem(-LHS, -RHS, Quotient, Remainder);...

...true argument made no difference. Other ideas anyone? My only other clue is that bits = 64. Thanks, Preston > I wrote the following bit of code > > static APInt FloorOfQuotient(APInt a, APInt b) { > unsigned bits = a.getBitWidth(); > APInt q(bits, 1), r(bits, 1); > APInt::sdivrem(a, b, q, r); > errs() << "sdivrem(" << a << ", " << b << ") = (" << q << ", " << r << ")\n"; > if (r == 0) > return q; > else { > if ((a.sgt(0) && b.sgt(0)) || &gt...

Hi Renato, > * Have some call-back mechanism, possibly upon a flag > (HasSpecialDivRemLowering), and update the remainder result If you setOperationAction on SDIVREM and UDIVREM to Custom you can expand the rtlib call appropriately yourself. There's precedent for sincos on Darwin systems (both ARM and x86) and in AArch64 for basically every operation on fp128. Cheers. Tim.

...already legal action). - Expansion - Promotion - Custom Expanding a node will lead to one of two things - the operation will be split into several equivalent smaller operations (i.e. 64-bit mul => two 32-bit multiplications), or it will be expanded into a different operation(s) (i.e. SDIVREM => SDIV + SREM or a runtime library call). This can be ambiguous - should a 128-bit SDIVREM be expanded into two 64-bit SDIVREMs or a 128-bit libcall. It would be useful for LLVM to distinguish between these two operations - i.e. instead of LegalizeAction::Expand, we have LegalizeAction::Expan...

...lInfo.second, FIPtr, MachinePointerInfo(), false, false, false, 0); Since I don't want to add a target-specific condition there, and I found no hierarchy for DAGLegalize, I'm wondering what's the best approach. Two options could be: * Creating a feature (HasDivRemRegister or whatever) and hard-code AEABI together with the hard-coded GNU * Have some call-back mechanism, possibly upon a flag (HasSpecialDivRemLowering), and update the remainder result Both are ugly... :( Is there anything like that elsewhere, that would hopefully be implemented inside ARM...

I’m hitting TableGen errors trying to match the smullohi <lhs> <rhs> node in TableGen. smullohi returns two results, which is the problem. I am not sure how to match against multiple results. The only other nodes to return two operands are umullohi, udivrem, and sdivrem. There are no examples of these in TableGen in tree. The closest I can get is this: set (R1, R0, (umullohi GPR8:$lhs, GPR8:$rhs)) Which fails: Assertion failed: (Ops.size() >= NumSrcResults && "Didn't provide enough results"), function EmitResultCode, fi...

...ions. In this code, for example, * if (isa<SCEVConstant>(delta) && isa<SCEVConstant>(srcCoeff)) { const SCEVConstant *constDelta = cast<SCEVConstant>(delta); const SCEVConstant *constCoeff = cast<SCEVConstant>(srcCoeff); APInt distance, remainder; APInt::sdivrem(constDelta->getValue()->getValue(), constCoeff->getValue()->getValue(), distance, remainder); * Generally, this makes sense. But reading the documentation for APInt, it sounds like I must somehow ensure that the representations ofconstDelta and cons...

I'm trying to replace SDIvRem (whch returns two i16 types) with a custom that returns i32 or i16. I am getting the Assertion (!Node || ResNo < Node->getNumValues() && "Invalid result number for the given node!") Seems that it doesn't like returning one value but how do you return more than one value...

Ignore the suggested fix in my earlier post. How about this? diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 20c81c3..b8ebf42 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1632,10 +1632,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, if (!Subtarget.is64Bit()) { // These

...I’m hitting TableGen errors trying to match the smullohi <lhs> <rhs> node > in TableGen. > > smullohi returns two results, which is the problem. I am not sure how to > match against multiple results. The only other nodes to return two operands > are umullohi, udivrem, and sdivrem. There are no examples of these in > TableGen in tree. > > The closest I can get is this: > > set (R1, R0, (umullohi GPR8:$lhs, GPR8:$rhs)) > > > As far as I know, you cannot define a tablegen pattern with multiple > results, and need to use C++ matching. I’m kind...