search for: sdeps

Andy, et al., In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this: if (!ExitSU.isPred(SU)) // Push store's up a bit to avoid them getting in between cmp // and branches. ExitSU.addPred(SDep(SU, SDep::Artificial)); This code does not seem to be in any way specific to compares; and in any case, at least on the PPC A2, scheduling stores in

On Jan 17, 2014, at 4:03 PM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 17, 2014, at 3:54 PM, Hal Finkel <hfinkel at anl.gov> wrote: > >> Andy, et al., >> >> In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this: >> >> if (!ExitSU.isPred(SU)) >> // Push store's up a bit to avoid them

...added, sorry for duplicated message. Hi list, Could someone help me to understand the internal data dependecy structure used by the scheduler ? As far as I can see in /lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp, SUnit nodes are created to wrap SDNodes with scheduling related information and SDeps represent all kind of dependencies between them. Nevertheless, I cannot figure out the graphical form of such structure. For example, in a simple SDep::Data dependency like the following one: Node1: def reg1 Node2: use reg1 Is Node1 the predecessor of Node2 or viceversa ? Regards, Ivan

Andy, I traced my problem to this point: In ScheduleDAGInstrs.cpp we have the following function: /// addVRegDefDeps - Add register output and data dependencies from this SUnit /// to instructions that occur later in the same scheduling region if they read /// from or write to the virtual register defined at OperIdx. /// /// TODO: Hoist loop induction variable increments. This has to be ///

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > >

Hi All, While reading LLVM source code, sometimes I am wondering when should we use auto instead of iterator/const_iterator. I want to use the patch [1] I sent before as an example. Could someone give me advice/guideline here? Also, I have another question. Sometimes the for-loop uses const_iterator, say for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();

Andy, Thanks for reply. I was able to trace the problem to the MI DAG dep constructor. See this: SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 # preds left : 0 # succs left : 0 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;

Hi list, Could anyone help me to roughly understand the internal data dependecy structure used by the scheduler ? As far as I can see in /lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp, SUnit nodes are created to wrap SDNodes with scheduling related information and SDeps represent all kind of dependencies between them. Nevertheless, I cannot figure out the graphical form of such structure. For example, in a simple SDep::Data dependency like the following one: Node1: def reg1 Node2: use reg1 Is Node1 the predecessor of Node2 or viceversa ? Ivan

Andy, You are probably right here - look at this - before phi elimination this code looks much more sane: # *** IR Dump After Live Variable Analysis ***: # Machine code for function push: SSA Function Live Outs: %R0 BB#0: derived from LLVM BB %entry %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4

...ckend handles condition codes pretty much like X86 and I remember I didn't get it to work without defining the allocation_order_end() function in RegisterInfo.td Anyway, I have no idea if this solution is ok for the general case, maybe the implicit defs information should rather be put into the SDeps when they are created? Regards, Christian -- please ignore: CONFIDENTIAL NOTICE: The contents of this message, including any attachments, are confidential and are intended solely for the use of the person or entity to whom the message was addressed. If you are not the intended recipient o...

...hether it is a good design and how best to move > it upstream. It looks like the fundamentals of the scheduler haven't > changed much from 2.9 to 3.1 so that makes it a bit easier. We plan to move to the MachineScheduler by 3.2. The structure is: ScheduleDAG: Abstract DAG of SUnits and SDeps | v ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI Delimit the current "region" of code being scheduled. | v ScheduleDAGMI: Concrete implementation that supports both top-down and bottom-up scheduling with live inter...

Hi, On 06/18/2011 06:26 AM, Benjamin Müller wrote: > i created a Function Pass to retrieve the Control/Data Flow Graph from > a simple program, > now i would like to statically schedule the Instructions. Is this > possible by starting to modify the SelectionDAG Files ? > Or can i even build a "standalone" custom scheduler? > Thank you very much for any tipps. You

Andrew Trick <atrick at apple.com> writes: > We plan to move to the MachineScheduler by 3.2. The structure is: How hard will this be to backport to 3.1? Has woprk on this started yet? > ScheduleDAG: Abstract DAG of SUnits and SDeps > | > v > ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI > Delimit the current "region" of code being scheduled. > | > v > ScheduleDAGMI: Concrete implementation that supports both top-down and bottom-up schedu...

Hi there, i created a Function Pass to retrieve the Control/Data Flow Graph from a simple program, now i would like to statically schedule the Instructions. Is this possible by starting to modify the SelectionDAG Files ? Or can i even build a "standalone" custom scheduler? Thank you very much for any tipps. Ben

Hey Everyone, I'd like to begin a project to rework the scheduler to address some problems we've discovered on this end. The goal is to get a more configurable/flexible scheduler while simplifying maintenance by separating policy from implementation to get independent and interchangeable parts. This is going to be challenging because we are still stuck on LLVM 2.9. We will be upgrading

...tty much > like X86 and I remember I didn't get it to work without defining the > allocation_order_end() function in RegisterInfo.td > Anyway, I have no idea if this solution is ok for the general case, > maybe the implicit defs information should rather be put into the > SDeps when they are created? > > Regards, > Christian > > -- > > > > > > > > please ignore: > > CONFIDENTIAL NOTICE: The contents of this message, including any > attachments, are confidential and are intended solely for the use of > the person or en...

Hello again, Sorry -- I think I found the problem somewhere else. I was a bit confused and missed the fact that adjustChainDeps() is called a few lines down and does just what I wanted :-) I would like to instead ask another question: Why is I->isCtrl() used in code like // Iterate over chain dependencies only. for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E =

> Please try it out, run tests, build your favourite projects and file > bugs about anything that needs to be fixed, marking them as blockers > of http://llvm.org/pr31622. I have encountered very long compile times for three large source files containing generated/unrolled code at -O1. We are talking about 10+ hours here without completing, so it looks very much like an endless loop. The

...woprk on this started > yet? In my previous message I outlined the steps that I would take to bring up the new scheduler. I'm about to checkin the register pressure reducing scheduler. The next step will be plugging in the target itinerary. >> ScheduleDAG: Abstract DAG of SUnits and SDeps >> | >> v >> ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI >> Delimit the current "region" of code being scheduled. >> | >> v >> ScheduleDAGMI: Concrete implementation that supports both top-do...

Sure I will split it and put it in two patches. Give me few hours. I need to test those patches. Sirish On 4/19/2012 8:40 AM, Tom Stellard wrote: > On Wed, Apr 18, 2012 at 11:18:05PM -0500, Sirish Pande wrote: >> Hi, >> >> Here's a patch for Hexagon Packetizer for review. This patch does >> not yield any warnings. >> > Would it be possible to split this