search for: sdep

Andy, et al., In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this: if (!ExitSU.isPred(SU)) // Push store's up a bit to avoid them getting in between cmp // and branches. ExitSU.addPred(SDep(SU, SDep::Artificial)); This code does not seem to be in any way specific to compares; and in any case, at least on the PPC A2, scheduling stores in between the compare and the branch would not be a bad thing (because the core is in order, and the compare has a 2-cycle latency, so if there is noth...

...ndy, et al., >> >> In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this: >> >> if (!ExitSU.isPred(SU)) >> // Push store's up a bit to avoid them getting in between cmp >> // and branches. >> ExitSU.addPred(SDep(SU, SDep::Artificial)); >> >> This code does not seem to be in any way specific to compares; and in any case, at least on the PPC A2, scheduling stores in between the compare and the branch would not be a bad thing (because the core is in order, and the compare has a 2-cycle latency, s...

...added, sorry for duplicated message. Hi list, Could someone help me to understand the internal data dependecy structure used by the scheduler ? As far as I can see in /lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp, SUnit nodes are created to wrap SDNodes with scheduling related information and SDeps represent all kind of dependencies between them. Nevertheless, I cannot figure out the graphical form of such structure. For example, in a simple SDep::Data dependency like the following one: Node1: def reg1 Node2: use reg1 Is Node1 the predecessor of Node2 or viceversa ? Regards, Ivan

...insert(VReg2SUnit(Reg, SU)); else { SUnit *DefSU = DefI->SU; if (DefSU != SU && DefSU != &ExitSU) { unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx, DefSU->getInstr()); DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg)); } DefI->SU = SU; } } So if this early exit is taken: // SSA defs do not have output/anti dependencies. // The current operand is a def, so we have at least one. if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) return; we do not ever...

...oid ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { > ... > // Add antidependence to the following def of the vreg it uses. > VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); > if (DefI != VRegDefs.end() && DefI->SU != SU) > DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg)); > > We will never find that def in VRegDefs.find(Reg) even though it exists. > > I know this has been working for a while, but I am still missing something > here. > What is this statement > > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())...

Hi All, While reading LLVM source code, sometimes I am wondering when should we use auto instead of iterator/const_iterator. I want to use the patch [1] I sent before as an example. Could someone give me advice/guideline here? Also, I have another question. Sometimes the for-loop uses const_iterator, say for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();

Andy, Thanks for reply. I was able to trace the problem to the MI DAG dep constructor. See this: SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 # preds left : 0 # succs left : 0 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;

Hi list, Could anyone help me to roughly understand the internal data dependecy structure used by the scheduler ? As far as I can see in /lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp, SUnit nodes are created to wrap SDNodes with scheduling related information and SDeps represent all kind of dependencies between them. Nevertheless, I cannot figure out the graphical form of such structure. For example, in a simple SDep::Data dependency like the following one: Node1: def reg1 Node2: use reg1 Is Node1 the predecessor of Node2 or viceversa ? Ivan

...y for another MI here: void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { ... // Add antidependence to the following def of the vreg it uses. VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); if (DefI != VRegDefs.end() && DefI->SU != SU) DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg)); We will never find that def in VRegDefs.find(Reg) even though it exists. I know this has been working for a while, but I am still missing something here. What is this statement if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) should guarantee? From it there must b...

...ckend handles condition codes pretty much like X86 and I remember I didn't get it to work without defining the allocation_order_end() function in RegisterInfo.td Anyway, I have no idea if this solution is ok for the general case, maybe the implicit defs information should rather be put into the SDeps when they are created? Regards, Christian -- please ignore: CONFIDENTIAL NOTICE: The contents of this message, including any attachments, are confidential and are intended solely for the use of the person or entity to whom the message was addressed. If you are not the intended recipient...

...hether it is a good design and how best to move > it upstream. It looks like the fundamentals of the scheduler haven't > changed much from 2.9 to 3.1 so that makes it a bit easier. We plan to move to the MachineScheduler by 3.2. The structure is: ScheduleDAG: Abstract DAG of SUnits and SDeps | v ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI Delimit the current "region" of code being scheduled. | v ScheduleDAGMI: Concrete implementation that supports both top-down and bottom-up scheduling with live inte...

Hi, On 06/18/2011 06:26 AM, Benjamin Müller wrote: > i created a Function Pass to retrieve the Control/Data Flow Graph from > a simple program, > now i would like to statically schedule the Instructions. Is this > possible by starting to modify the SelectionDAG Files ? > Or can i even build a "standalone" custom scheduler? > Thank you very much for any tipps. You

Andrew Trick <atrick at apple.com> writes: > We plan to move to the MachineScheduler by 3.2. The structure is: How hard will this be to backport to 3.1? Has woprk on this started yet? > ScheduleDAG: Abstract DAG of SUnits and SDeps > | > v > ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI > Delimit the current "region" of code being scheduled. > | > v > ScheduleDAGMI: Concrete implementation that supports both top-down and bottom-up sched...

Hi there, i created a Function Pass to retrieve the Control/Data Flow Graph from a simple program, now i would like to statically schedule the Instructions. Is this possible by starting to modify the SelectionDAG Files ? Or can i even build a "standalone" custom scheduler? Thank you very much for any tipps. Ben

Hey Everyone, I'd like to begin a project to rework the scheduler to address some problems we've discovered on this end. The goal is to get a more configurable/flexible scheduler while simplifying maintenance by separating policy from implementation to get independent and interchangeable parts. This is going to be challenging because we are still stuck on LLVM 2.9. We will be upgrading

...tty much > like X86 and I remember I didn't get it to work without defining the > allocation_order_end() function in RegisterInfo.td > Anyway, I have no idea if this solution is ok for the general case, > maybe the implicit defs information should rather be put into the > SDeps when they are created? > > Regards, > Christian > > -- > > > > > > > > please ignore: > > CONFIDENTIAL NOTICE: The contents of this message, including any > attachments, are confidential and are intended solely for the use of > the person or e...

...only. for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end(); I != E; ++I) if (I->isCtrl()) iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited); ? I thought only chain edges are relevant, and would instead use if (J->getKind() == SDep::Order) I got strange edges, from memory accesses to normal operation instructions that do not touch memory, because also anti and output edges are followed. Best regards, Jonas Paulsson -----Original Message----- From: Jonas Paulsson Sent: den 13 december 2014 14:47 To: 'Hal Finkel'...

...ithout completing, so it looks very much like an endless loop. The processes are using 15, 22 and 27 GB of memory but do not appear to grow further. This worked fine in the past, so appears to be a regression. These stacks seem to be prevalent: #0 0x0000000001850588 in llvm::SUnit::addPred(llvm::SDep const&, bool) () #1 0x0000000001855265 in llvm::ScheduleDAGInstrs::addChainDependency(llvm::SUnit*, llvm::SUnit*, unsigned int) () #2 0x0000000001855519 in llvm::ScheduleDAGInstrs::addChainDependencies(llvm::SUnit*, llvm::ScheduleDAGInstrs::Value2SUsMap&) () #3 0x000000000185f3ba in llvm...

...woprk on this started > yet? In my previous message I outlined the steps that I would take to bring up the new scheduler. I'm about to checkin the register pressure reducing scheduler. The next step will be plugging in the target itinerary. >> ScheduleDAG: Abstract DAG of SUnits and SDeps >> | >> v >> ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI >> Delimit the current "region" of code being scheduled. >> | >> v >> ScheduleDAGMI: Concrete implementation that supports both top-d...

...- Is it legal to prune dependece between SUI >> + // and SUJ. >> + bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ); >> + >> + MachineBasicBlock::iterator addToPacket(MachineInstr *MI); >> + private: >> + bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg); >> + bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, >> + MachineBasicBlock::iterator&MII, >> + const TargetRegisterClass* RC); >> + bool CanPromoteToDotNew(MachineInstr* MI, SUnit* P...