Displaying 5 results from an estimated 5 matches for "scratchreg".
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scratch_reg
2014 Oct 10
2
[LLVMdev] eliminateFrameIndex
...er files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far.
I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this:
// frame pointer is in reg of class mytarget::ARegsRegClass
unsigned ScratchReg = MF.getRegInfo().createVirtualRegister(&mytarget::ARegsRegClass);
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
BuildMI(*MI.getParent(), II, dl, TII.get(mytarget::ADD_AReg), ScratchReg).addReg(FramePtr).addImm(Offset);
// Update the original instruction to use the scratch re...
2017 Apr 18
2
[RFC] Adding CPS call support
...architectures, you can emulate this (for example, you could lower an IR "call" to LEA+JMP on x86-64).
This is similar to what I was originally thinking, since the end goal of all of this is the following machine code for a call (I'll use an x86-64 example):
leaq _retpt(%rip), %scratchReg
movq %scratchReg, (%ghcSPReg)
jmp _bar
But, if we want to end up with the above machine code using a custom lowering of just the following IR instruction,
%retVals = cps call ghccc @bar (... args ...)
_without_ explicitly taking the block address and writing it to the GHC stack p...
2017 Apr 17
2
[RFC] Adding CPS call support
(Sorry for the 2nd email Eli, I forgot to reply-all).
> I'm not following how explicitly representing the return address of a call in the IR before isel actually solves any relevant issue. We already pass the return address implicitly as an argument to every call; you can retrieve it with llvm.returnaddress if you need it.
Unfortunately the @llvm.returnaddress intrinsic does not solve
2012 Nov 11
0
[LLVMdev] register scavenger
I ran into another issue with register scavenger.
In my case, I don't need a place on the stack for an emergency spill slot.
I have these free mips32 registers, that are not in general very useful
for other things, for the emergency spill slot. I can move to and from
mips16 (subset of mips32) registers and mips32 registers.
I also have a situation where I need two free registers so then
2012 Nov 11
2
[LLVMdev] register scavenger
You mean when I "explicity" use it by calling methods of register scavenger?
Right now I'm just allocating virtual registers that will be resolved by
the use of register scavenger and I'm also providing an override of the
virtual method saveScavengerRegister. In Mips16, I have an extra mips 32
register (not usually very useful since it can only be used
in a move instruction)