search for: scoreboardhazardcheck

...rride scheduling decisions. That logic is both difficult to maintain, and incompatible with the goal of defining a self-contained machine model.) It also made simple concepts like register bypass very difficult to express and poorly communicated the machine model. The implementation of itineraries (ScoreboardHazardChecker) also needlessly wastes compile time for all but a rare class of VLIW cpus. > Another question is if one could opt, which representation should me used to represent scheduling information for new targets? I can’t imagine why someone want to use itineraries for a new target. Maybe you have a...

Hi, >From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required

...isions. That logic is both difficult to maintain, and incompatible with > the goal of defining a self-contained machine model.) It also made simple > concepts like register bypass very difficult to express and poorly > communicated the machine model. The implementation of itineraries > (ScoreboardHazardChecker) also needlessly wastes compile time for all but a > rare class of VLIW cpus. > > > Another question is if one could opt, which representation should me > used to represent scheduling information for new targets? > > I can’t imagine why someone want to use itineraries for a n...