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...case (see example below): ``` def ZeroIdiomWrite : SchedWriteRes<[]> { let Latency = 0; } def ZeroIdiom : SchedPredicate<[{ MI->getOpcode() == X86::XORrr && MI->getOperand(0).getReg() == MI->getOperand(1).getReg() }]>; def WriteXOR : SchedWriteVariant<[ SchedVar<ZeroIdiom, [ZeroIdiomWrite], SchedVar<NoSchedPred, [WriteALU] >; ``` Problems with the current design -------------------------------- A SchedPredicate is essentially a custom block of C++ code used by the SubtargetEmitter to generate a condition through a boolean expression. A Sche...

...he wakeup signal used to wakeup the second micro-op seems to be a demand that the micro-op issues in that cycle rather than permission to issue when it's convenient. Is it possible to use other instructions already scheduled for the same cycle as part of the evaluation of a SchedPredicate in a SchedVariant? I've got a class of instructions (mostly simple addition) that can dispatch to two different reservation stations (ALQ and AGQ), both of which have a suitable pipeline with the same latency. The dispatch stage can dispatch two instructions per cycle. When it has one instruction from this c...

...cycle latency pipeline called LDST. Three cycles after issue, the LDST pipeline wakes up the FPQ micro-op, which writes the result of the load back to the register file. Is it possible to use other instructions already scheduled for the same cycle as part of the evaluation of a SchedPredicate in a SchedVariant? I've got a class of instructions (mostly simple addition) that can dispatch to two different reservation stations (ALQ and AGQ), both of which have a suitable pipeline with the same latency. The dispatch stage can dispatch two instructions per cycle. When it has one instruction from this c...