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2013 Dec 15
3
[LLVMdev] Question about Pre-RA-schedule in LLVM3.3
...However, for 3th and 4th instructions, they should be allocated different register from the second instruction.
So, I insert a breakpoint in BuildSchedGraph function in ScheduleDAGSNodes.cpp to debug the source code.
Then I get schedule graph of this basic block:
Like the above graph, Pre-RA-sched(ScheduleRRList.cpp) is unable to insert the 3th SDNode(load2 instruction) between the first SDNode(load1 Instruction) and the second store1 SDNode.
Then in the register allocation step, the pair instruction are allocated same register.
However, if we build a schedule graph like the following:
I think that Pre-R...