search for: schedulepostratdlist

Hi All, While reading SchedulePostRATDList::ListScheduleTopDown() [1], I find SchedulingPriorityQueue::dump has an empty implementation. Therefore, the following debug dump basically outputs nothing. DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this)); Not sure why we want this. Is it intended...

...rs that does the following: 1. Find candidate nodes in the DAG, and speculatively modify the node (nodes). 2. After modification, try to compute the scheduled cycles of the region. 3. If the cycle number improves, go back to 1. to find the next candidate node. I am thinking using SchedulePostRATDList's top-down algorithm to calculate the cycles needed for the region's execution. However, it decomposes the schedule DAG while calculating the cycles --- In my case I want to keep the DAG so that we don't need to construct it again in the following steps. So my question is: is there a w...

...he >> node (nodes). >> >> 2. After modification, try to compute the scheduled cycles of the >> region. >> >> 3. If the cycle number improves, go back to 1. to find the next >> candidate node. >> >> >> >> I am thinking using SchedulePostRATDList’s top-down algorithm to >> calculate the cycles needed for the region’s execution. However, it >> decomposes the schedule DAG while calculating the cycles --- In my case I >> want to keep the DAG so that we don’t need to construct it again in the >> following steps. >>...

...; > - Pre 2008: SelectionDAGISel pass creates the ScheduleDAG from the > SelectionDAG at the end of instruction selection > - ScheduleDAG works on SelectionDAG Nodes (SDNodes) > - Circa 2008: Post Register > > Allocation pass added for > > instruction selection ( SchedulePostRATDList > > works on MachineInstrs) > > - Circa 2012: MIScheduler > > (ScheduleDAGMI) added as > > separate pass for pre-RA > > scheduling > > - Circa 2014: MIScheduler > > adapted to optionally replace > > PostRA Scheduler > > In the presentation...

...roach scheduling in LLVM over the years: * Pre 2008: SelectionDAGISel pass creates the ScheduleDAG from the SelectionDAG at the end of instruction selection * ScheduleDAG works on SelectionDAG Nodes (SDNodes) * Circa 2008: Post Register Allocation pass added for instruction selection ( SchedulePostRATDList works on MachineInstrs) * Circa 2012: MIScheduler (ScheduleDAGMI) added as separate pass for pre-RA scheduling * Circa 2014: MIScheduler adapted to optionally replace PostRA Scheduler In the presentation he goes with defining a subclass of SchedMachineModel in the schedule .td file. And...

...the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the argument Stalls = 0. This is no surprise since in PostRASchedulerList.cpp we have only one call to it, in method SchedulePostRATDList::ListScheduleTopDown(): ScheduleHazardRecognizer::HazardType HT = HazardRec->getHazardType(CurSUnit, 0/*no stalls*/); Let me state what I have added to my back end to enable scheduling with hazards: - inspiring from lib/Target/PowerPC/PPCHazardRecognizers.h, I have c...

Hello. I am progressing a bit with difficulty with the post RA scheduler (PostRASchedulerList.cpp with ScoreboardHazardRecognizer) - the problem I have is that it doesn't advance at the next available instruction when the overridden ScoreboardHazardRecognizer::getHazardType() method returns NoopHazard and it gets stuck at the same instruction (store in my runs). Just to make sure: