Displaying 5 results from an estimated 5 matches for "scheduledagvliw".
2012 Jun 06
2
[LLVMdev] Instruction bundles before RA: Rematerialization
...*before* RA to
model certain constraints, e.g. the exposed one by Tzu-Chien a while ago
in his thread
http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004798.html
In order to build bundles, we have added a new bottom-up MIScheduler,
right after reg coalescing, which behaves much like ScheduleDAGVLIW but
without hazard recognizing. Due to some tricky instructions, we cannot
schedule on the DAG. Bundles are built at exitRegion() in the scheduling
process and the live interval information is updated correctly. After
this, the RA is aware of bundles, at least from a LiveInterval point of
view...
2012 Jun 06
0
[LLVMdev] Instruction bundles before RA: Rematerialization
...The bundle support in the tree should handle constraints like that. The register allocator basically sees bundles as single instructions when computing interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves much like ScheduleDAGVLIW but
> without hazard recognizing. Due to some tricky instructions, we cannot
> schedule on the DAG. Bundles are built at exitRegion() in the scheduling
> process and the live interval information is updated correctly. After
> this, the RA is aware of bundles, at least from a LiveInt...
2012 Jun 07
2
[LLVMdev] Instruction bundles before RA: Rematerialization
...the tree should handle constraints like that.
The register allocator basically sees bundles as single instructions
when computing interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves much like
ScheduleDAGVLIW but
> without hazard recognizing. Due to some tricky instructions, we
cannot
> schedule on the DAG. Bundles are built at exitRegion() in the
scheduling
> process and the live interval information is updated correctly. After
> this, the RA is aware of bundles,...
2012 Jun 07
0
[LLVMdev] Instruction bundles before RA: Rematerialization
...The bundle support in the tree should handle constraints like that. The register allocator basically sees bundles as single instructions when computing interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves much like ScheduleDAGVLIW but
> without hazard recognizing. Due to some tricky instructions, we cannot
> schedule on the DAG. Bundles are built at exitRegion() in the scheduling
> process and the live interval information is updated correctly. After
> this, the RA is aware of bundles, at least from a LiveInterva...
2015 Jul 29
1
[LLVMdev] Error when i am using command make -j4 command in cygwin to compile safecode
...d subtarget information with tblgen
llvm[2]: Compiling LoopInfo.cpp for Release+Asserts build
llvm[3]: Compiling ScheduleDAGSDNodes.cpp for Release+Asserts build
llvm[3]: Compiling SimplifyCFG.cpp for Release+Asserts build
llvm[2]: Compiling LoopPass.cpp for Release+Asserts build
llvm[3]: Compiling ScheduleDAGVLIW.cpp for Release+Asserts build
llvm[2]: Compiling MemDepPrinter.cpp for Release+Asserts build
llvm[3]: Compiling X86AsmPrinter.cpp for Release+Asserts build
llvm[3]: Compiling SelectionDAG.cpp for Release+Asserts build
llvm[2]: Compiling MemDerefPrinter.cpp for Release+Asserts build
llvm[2]: Compili...