search for: scheduledagmilive

Hi All, The description of ScheduleDAGMILive [1] says: ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure. Does the live interval and register pressure part of ScheduleDAGMILive mean the subclass of ScheduleDAGMILive is a pre-RA schedu...

Hi, Matthias. >From the class hierarchy, ScheduleDAGMILive is also a ScheduleDAGMI. I am wondering if there will be any problem if we use subclass of ScheduleDAGMILive as post-RA scheduler? The best case is ScheduleDAGMILive just waste time on book-keeping register pressure, but I am not sure if we can still do those book-keeping after RA. Talk about post...

...::ScheduleDAGInstrs::addChainDependencies(llvm::SUnit*, llvm::ScheduleDAGInstrs::Value2SUsMap&) () #3 0x000000000185f3ba in llvm::ScheduleDAGInstrs::buildSchedGraph(llvm::AAResults*, llvm::RegPressureTracker*, llvm::PressureDiffs*, llvm::LiveIntervals*, bool) () #4 0x00000000017d3c89 in llvm::ScheduleDAGMILive::buildDAGWithRegPressure() () #5 0x00000000017d3d13 in llvm::ScheduleDAGMILive::schedule() () #6 0x00000000017d015e in (anonymous namespace)::MachineSchedulerBase::scheduleRegions(llvm::ScheduleDAGInstrs&, bool) [clone .isra.553] () #7 0x00000000017d2c11 in (anonymous namespace)::MachineSche...

...re is a lot of output and at this point I'm not sure what is important and what is not. I'm trying to solve this problem in small steps, so if asked I can certainly provide more information. The first error that I see during compilation is lib/CodeGen/MachineScheduler.cpp:1165: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit*, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Another important detail is that we are running clang-3.5. I know it is old, but for now we are not allowed to switch to a newer version. I would greatly appreciate any...

...using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined in the block when walking through the operands for these instructions. The peak pressure printouts from ScheduleDAGMILive look like they are accounting for AH and AL being live because the corresponding pressure sets for these register classes are increased. In the mischeduler is there a way to discover that these two registers may be contributing to peak pressure in the block? Thanks, Austin Kerbow ---------...

...11:41 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 4/27/2016 12:10 PM, Rail Shafigulin via llvm-dev wrote: > >> >> The first error that I see during compilation is >> >> lib/CodeGen/MachineScheduler.cpp:1165: void >> llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit*, bool): Assertion >> `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. >> > > This happens on Hexagon too. I have a patch for review: > http://reviews.llvm.org/D19438 > > -Krzysztof > > > -- > Qualco...

...llvm-dev at lists.llvm.org>> wrote: >> >> On 4/27/2016 12:10 PM, Rail Shafigulin via llvm-dev wrote: >> >> >> The first error that I see during compilation is >> >> lib/CodeGen/MachineScheduler.cpp:1165: void >> llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit*, bool): Assertion >> `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. >> >> >> This happens on Hexagon too. I have a patch for review: >> http://reviews.llvm.org/D19438 >> >>...

...annotated as noalias to basically remove loop-carried dependencies so that I can reorder them for efficient scheduling. But when I look at Schedule DAG, For vec_add I see something like this (note BotQ.A, scheduler can choose any of those => no loop carried dependence): - Latency limited. ** ScheduleDAGMILive::schedule picking next node Queue BotQ.P: Queue BotQ.A: 16 15 11 7 3 Cand SU(16) ORDER Pick Bot ORDER For main, at best I see something like this: ** ScheduleDAGMILive::schedule picking next node Cycle: 45 BotQ.A Queue BotQ.P: Queue BotQ.A: 12 13 Cand SU(12) ORDER Cand SU(13) ORDER In theor...

...rg>>> wrote: > > On 4/27/2016 12:10 PM, Rail Shafigulin via llvm-dev wrote: > > > The first error that I see during compilation is > > lib/CodeGen/MachineScheduler.cpp:1165: void > llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit*, > bool): Assertion > `TopRPTracker.getPos() == CurrentTop && "out of > sync"' failed. > > > This happens on Hexagon too. I have a patch for review: > http:...

Hi Jeroen, That's great! I was trying to use the patch, what's the latest version of the project we could apply it on? Hi Neil, That seems like what I can do as well! Do you happen to have some examples lying around? Maybe a pointer to the planned presentation, if that's okay? Thank you, Bandhav On Mon, Jun 22, 2020 at 1:55 AM Neil Henning <neil.henning at unity3d.com>