search for: scheduledagmi

Hi, Matthias. >From the class hierarchy, ScheduleDAGMILive is also a ScheduleDAGMI. I am wondering if there will be any problem if we use subclass of ScheduleDAGMILive as post-RA scheduler? The best case is ScheduleDAGMILive just waste time on book-keeping register pressure, but I am not sure if we can still do those book-keeping after RA. Talk about...

On Jun 3, 2013, at 9:42 AM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > Hi Jakob, > > thanks for the advice. I'll do as you suggest and make sure that CCR is never live. > > I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of

Hi All, The description of ScheduleDAGMILive [1] says: ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure. Does the live interval and register pressure part of ScheduleDAGMILive mean the subclass of ScheduleDAGMILive is a pre-RA sc...

...it at a high level. You could start off like PPC with minimal customization, but eventually you may want something in between--provide a custom MachineSchedStrategy: class MyScheduler : public MachineSchedStrategy {...} namespace llvm { ScheduleDAGInstrs *createMySched(MachineSchedContext *C) { ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new MyScheduler()); DAG->addMutation(new MyDAGMutation()); return DAG; } } // namespace llvm static MachineSchedRegistry MySchedRegistry("mysched", "Custom My scheduler.", createMySched); -Andy > Thanks, > Fraser > > -- > Fr...

...like > PPC with minimal customization, but eventually you may want something > in between--provide a custom MachineSchedStrategy: > > class MyScheduler : public MachineSchedStrategy {...} > > namespace llvm { > ScheduleDAGInstrs *createMySched(MachineSchedContext *C) { > ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new MyScheduler()); > DAG->addMutation(new MyDAGMutation()); > return DAG; > } > } // namespace llvm > > static MachineSchedRegistry > MySchedRegistry("mysched", "Custom My scheduler.", createMySched); > > -Andy >...

I have an instruction that takes no operands, and produces two results, in two consecutive cycles. I tried both of the following to my Schedule.td file: InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, [FuncU]>], [1, 2]>, From what I can see in examples, these say that the first

Hi Jakob, thanks for the advice. I'll do as you suggest and make sure that CCR is never live. I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of cmp instruction so I might need a lot of pseudos. That's what led me to wonder whether MachineInstrBundles might be a

...uling by default on x86. http://article.gmane.org/gmane.comp.compilers.llvm.devel/63242/match=machinescheduler I suggest integrating with the MachineScheduler pass. There are many places to plug in. MachineSchedRegistry provides the hook. At that point you can define your own ScheduleDAGInstrs or ScheduleDAGMI subclass. People who only want to define new heuristics should reuse ScheduleDAGMI directly and only define their own MachineSchedStrategy. > > - Our SPEC testing on x86-64 has shown a significant performance improvement of LLVM 3.3 relative to LLVM 2.9 (about 5% in geomean on INT2006 and 1...

...easier. We plan to move to the MachineScheduler by 3.2. The structure is: ScheduleDAG: Abstract DAG of SUnits and SDeps | v ScheduleDAGInstrs: Build the DAG from MachineInstrs, each SUnit tied to an MI Delimit the current "region" of code being scheduled. | v ScheduleDAGMI: Concrete implementation that supports both top-down and bottom-up scheduling with live interval update. It divides the region into three zones: Top-scheduled, bottom-scheduled, and unscheduled. The ScheduleDAGMI constructor takes an instance of MachineSchedStrategy....

...ed code, which is currently required to be post-RA, I think?). Hence, I basically created a new post-RA scheduler similar to MI scheduler, which does bundling and handles delay slots and NOOP insertion. The downside is that there is a lot of code duplication, since the MI scheduler usually uses ScheduleDAGMI and not the more generic ScheduleDAGInstr at the interfaces. So here are my questions: - Are there any plans for a (more generic) post-RA scheduler replacement, or the possibility to run the MI scheduler post-RA (i.e., without live variable analysis depenency), or is simply creating a comple...

Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that

...end of instruction selection > - ScheduleDAG works on SelectionDAG Nodes (SDNodes) > - Circa 2008: Post Register > > Allocation pass added for > > instruction selection ( SchedulePostRATDList > > works on MachineInstrs) > > - Circa 2012: MIScheduler > > (ScheduleDAGMI) added as > > separate pass for pre-RA > > scheduling > > - Circa 2014: MIScheduler > > adapted to optionally replace > > PostRA Scheduler > > In the presentation he goes with defining a subclass of SchedMachineModel > in the schedule .td file. And apparent...

Hey Everyone, I'd like to begin a project to rework the scheduler to address some problems we've discovered on this end. The goal is to get a more configurable/flexible scheduler while simplifying maintenance by separating policy from implementation to get independent and interchangeable parts. This is going to be challenging because we are still stuck on LLVM 2.9. We will be upgrading

...730, mf=...) at lib/CodeGen/MachineScheduler.cpp:263 #12 in llvm::MachineFunctionPass::runOnFunction (this=0x448c770, F=...) at lib/CodeGen/MachineFunctionPass.cpp:33 For the purpose of this question, you can assume HexagonMachineScheduler.cpp == MachineScheduler.cpp and VLIWMachineScheduler == ScheduleDAGMI The instruction being moved is a simple call: let isCall = 1, neverHasSideEffects = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1, USR] in { def CALLv3 : JInst<(outs), (ins calltarget:$dst), "call $dst", []>, Re...

...uling by default on x86.  http://article.gmane.org/gmane.comp.compilers.llvm.devel/63242/match=machinescheduler I suggest integrating with the MachineScheduler pass. There are many places to plug in. MachineSchedRegistry provides the hook. At that point you can define your own ScheduleDAGInstrs or ScheduleDAGMI subclass. People who only want to define new heuristics should reuse ScheduleDAGMI directly and only define their own MachineSchedStrategy. > >- Our SPEC testing on x86-64 has shown a significant performance improvement of LLVM 3.3 relative to LLVM 2.9 (about 5% in geomean on INT2006 and 1...

...strategy defines the priority queues, you can do whatever you want for your register pressure heuristics. From scanning the full queue each time with dynamic heuristics, to resorting, to dynamically deferring nodes... Note that the register pressure tracking is handled outside of the strategy, in ScheduleDAGMI. So you get this for free without duplication. However, querying pressure change for a candidate is done by the strategy. The generic interface, getMaxPressureDelta(), is very clunky now. I’m going to improve it, but If you’re writing a target specific strategy, it’s probably easier to directly qu...

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has

...and Hexagon. If there are no objections I’d like to move x86 and armv7 ASAP. Leaving it disabled is becoming more of a maintenance burden. Please see my llvm-dev list messages to Ghassan yesterday. MI Scheduler is pass that just provides a place to do scheduling and a large toolbox to do it with. ScheduleDAGMI is a list scheduler driver, and the GenericScheduler strategy attempts to balance register pressure with latency. In my opinion getting the right register pressure vs latency balance is easy to do at a given point in time for a small benchmark suite, but very, very hard to do in general with a desi...

...ions I’d like to move x86 > and armv7 ASAP. Leaving it disabled is becoming more of a maintenance > burden. > > > Please see my llvm-dev list messages to Ghassan yesterday. MI Scheduler is > pass that just provides a place to do scheduling and a large toolbox to do > it with. ScheduleDAGMI is a list scheduler driver, and the GenericScheduler > strategy attempts to balance register pressure with latency. In my opinion > getting the right register pressure vs latency balance is easy to do at a > given point in time for a small benchmark suite, but very, very hard to do > in...

Thanks  Kryzstof, I will look at it. Is there any class that I should look at it ? What about Dataflow.h ? Since I am kind of new, I want to know which classes can help me quicker.    =========================================== Phone : 82-42-860-1838 Fax : 82-42-860-6790 Cell Phone: 82-10-7599-1981 =========================================== --- On Sat, 11/3/12, Krzysztof Parzyszek