search for: scheduledaglist

Displaying 8 results from an estimated 8 matches for "scheduledaglist".

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2006 May 16
0
[LLVMdev] Re: Release 1.6 LLVM-Cfrontend build error on cygwin
...k. You wrote Tuesday, May 16, 2006, 6:03:14 PM: C> /netrel/src/binutils-20050610-1/bfd/cofflink.c:1926 C> make[2]: *** I've tracked this assertion some more deep. The problem is in LLVMSelectionDAG.o file. If I run the next lines, I've got and assertion: ld -r -o LLVMSelectionDAG.o ScheduleDAGList.o ScheduleDAGRRList.o ld -o llc LLVMSelectionDAG.o If I remove one of the SheduleDAG* files from the full list of objects, LLVMSelectionDAG.o is built from, the assertion is not longer triggered. Any ideas, why? I think, there is duplicate symbols somewhere, but I'm not sure. -- With best r...
2008 Jun 10
4
[LLVMdev] Compiling llvm libraries to run on iPhone
...rwin –target=arm-apple-darwin –enable-optimized –enable-targets=arm I run make, including an override for TBLGEN (because I obviously can’t run the native ARM tblgen): make ENABLE_OPTIMIZED=1 TBLGEN=/usr/local/bin/tblgen All goes very well until I get the following error: llvm[3]: Compiling ScheduleDAGList.cpp for Release build llvm[3]: Compiling ScheduleDAGRRList.cpp for Release build llvm[3]: Compiling SelectionDAG.cpp for Release build llvm[3]: Compiling SelectionDAGISel.cpp for Release build /var/folders/Xq/XqzGACxLHWq4Af0cQbEMdE+++TI/-Tmp-//cc6xGQcn.s:unknown:immediate value (-288) too large...
2009 Feb 06
2
[LLVMdev] list-td scheduler asserts on targets with implicitly defined registers
Hi, I just switched to the 2.5 release branch and noticed that llc runs into the following assert in ScheduleDAGList::ScheduleNodeTopDown() using our custom backend: assert(!I->isAssignedRegDep() && "The list-td scheduler doesn't yet support physreg dependencies!"); It turns out that the register dependency concerns the condition code register which is modeled as an impli...
2006 May 14
7
[LLVMdev] Release 1.6 LLVM-Cfrontend build error on cygwin
Dear llvmdev, I am new to LLVM , but have a task on writing a LLVM backend to generate some architecture specific assembly file. Here is my cygwin build setting: GCC 3.4.4 , BIN UTILITY 2.15 ,and all other packages of the right version listed on the LLVM Getting Started doc. I have successfully built Release 1.6 LLVM. All the tools has been installed there /usr/local/bin . But I
2008 Jun 11
0
[LLVMdev] Compiling llvm libraries to run on iPhone
...nable-optimized –enable-targets=arm > > I run make, including an override for TBLGEN (because I obviously can’t run the native ARM tblgen): > > make ENABLE_OPTIMIZED=1 TBLGEN=/usr/local/bin/tblgen > > All goes very well until I get the following error: > > llvm[3]: Compiling ScheduleDAGList.cpp for Release build > llvm[3]: Compiling ScheduleDAGRRList.cpp for Release build > llvm[3]: Compiling SelectionDAG.cpp for Release build > llvm[3]: Compiling SelectionDAGISel.cpp for Release build > /var/folders/Xq/XqzGACxLHWq4Af0cQbEMdE+++TI/-Tmp-//cc6xGQcn.s:unknown:immed iate value...
2009 Feb 06
0
[LLVMdev] list-td scheduler asserts on targets with implicitly defined registers
...class's copy cost. -1 means it's extremely expensive to copy registers in the particular register class. Evan On Feb 6, 2009, at 2:22 AM, Christian Sayer wrote: > Hi, > > I just switched to the 2.5 release branch and noticed that llc runs > into the following assert in ScheduleDAGList::ScheduleNodeTopDown() > using our custom backend: > > assert(!I->isAssignedRegDep() && > "The list-td scheduler doesn't yet support physreg > dependencies!"); > > It turns out that the register dependency concerns the condition >...
2011 Apr 14
3
[LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?
Hello, While trying to create back end in LLVM I have stumbled upon a problem I have trouble to get past, hopefully someone can give me hints on what I am doing wrong. The problem is that the assertion in the file ScheduleDAGList.cpp row 187 is triggered: "Negative latency". How does this happen? As background: My target has one issue unit, therefore my Schedule.td file only contain one functional unit. My instruction itineraries are defined to all take 1 machine cycle to complete (my target is fully pipeli...
2008 Jun 11
0
[LLVMdev] some warning from VS2005 (requested by gabor)
...rning C4244: 'initializing' : conversion from 'uint64_t' to 'unsigned int', possible loss of data ..\..\lib\CodeGen\SelectionDAG\ScheduleDAG.cpp(927) : warning C4244: 'initializing' : conversion from 'uint64_t' to 'unsigned int', possible loss of data ScheduleDAGList.cpp ScheduleDAGRRList.cpp SelectionDAG.cpp ..\..\lib\CodeGen\SelectionDAG\SelectionDAG.cpp(1303) : warning C4244: 'initializing' : conversion from 'uint64_t' to 'unsigned int', possible loss of data ..\..\lib\CodeGen\SelectionDAG\SelectionDAG.cpp(1321) : warning C4244: '...