Displaying 6 results from an estimated 6 matches for "scheduledagemit".
2008 Sep 13
2
[LLVMdev] Alignment of constant loads
...nment? We're not sure where this should be "fixed".
It looks like the best way to do this is to visit the handful of
places in legalize that create loads from constant pools and
add alignment parameters to the getLoad/getExtLoad calls.
If you move the handling of Alignment==0 out of ScheduleDAGEmit.cpp
and into SelectionDAG::getConstantPool, you can then have legalize
read the alignment from the node, instead of making its own
decision:
cast<ConstantPoolSDNode>(CPIdx)->getAlignment()
Dan
2008 Sep 15
0
[LLVMdev] Alignment of constant loads
Hi Dan,
> It looks like the best way to do this is to visit the handful of
> places in legalize that create loads from constant pools and
> add alignment parameters to the getLoad/getExtLoad calls.
>
> If you move the handling of Alignment==0 out of ScheduleDAGEmit.cpp
> and into SelectionDAG::getConstantPool, you can then have legalize
> read the alignment from the node, instead of making its own
> decision:
> cast<ConstantPoolSDNode>(CPIdx)->getAlignment()
>
>
I followed your suggestion but I've come across a bit of a sn...
2010 Nov 12
1
[LLVMdev] ScheduleDAG Question
I am tracking down a tricky bug involving select/CMOV and scheduling.
In my test, I have a float select that has to be implemented with a
diamond CFG by the scheduler. The high level
ScheduleDAGSDNodes::EmitSchedule does this:
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
[...]
Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
You need to specify sub-register == super-register, idx relationship.
See X86RegisterInfo.td:
def x86_subreg_8bit : PatLeaf<(i32 1)>;
def x86_subreg_16bit : PatLeaf<(i32 2)>;
def x86_subreg_32bit : PatLeaf<(i32 3)>;
def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL,
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>
> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
>
> > What’s the value produced by an INSERT_SUBREG node? Is it a chain?
>
>
> No, insert_subreg returns a value:
>
>
> v1 = insert_subreg v2, v3, idx
>
>
> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...P, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
class GR16_ ..... {
let SubRegClassList = [GR8];
}
Refer to below functions in ScheduleDAGEmit.cpp:
-----------------------------------------------
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;...