Displaying 8 results from an estimated 8 matches for "scheduleandemitdag".
2007 Apr 06
3
[LLVMdev] llc assertion failure
...; >&)+0x8b2)[0x86ab9fc]
/home/lefever/work/install/bin/llc(llvm::ScheduleDAG::EmitSchedule()+0x283)[0x86abf7d]
/home/lefever/work/install/bin/llc[0x861cada]
/home/lefever/work/install/bin/llc(llvm::ScheduleDAG::Run()+0x94)[0x86a9d6c]
/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::ScheduleAndEmitDAG(llvm::SelectionDAG&)+0x73)[0x863e64d]
/home/lefever/work/install/bin/llc[0x84edf05]
/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::CodeGenAndEmitDAG(llvm::SelectionDAG&)+0x13b)[0x863e7ab]
/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::SelectBasicBlock(llvm::BasicBloc...
2007 Apr 06
0
[LLVMdev] llc assertion failure
...0x86ab9fc]
> /home/lefever/work/install/bin/llc(llvm::ScheduleDAG::EmitSchedule()+0x283)[0x86abf7d]
> /home/lefever/work/install/bin/llc[0x861cada]
> /home/lefever/work/install/bin/llc(llvm::ScheduleDAG::Run()+0x94)[0x86a9d6c]
> /home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::ScheduleAndEmitDAG(llvm::SelectionDAG&)+0x73)[0x863e64d]
> /home/lefever/work/install/bin/llc[0x84edf05]
> /home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::CodeGenAndEmitDAG(llvm::SelectionDAG&)+0x13b)[0x863e7ab]
> /home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::SelectBasicBlock(...
2007 Apr 06
2
[LLVMdev] llc assertion failure
...gt;>/home/lefever/work/install/bin/llc(llvm::ScheduleDAG::EmitSchedule()+0x283)[0x86abf7d]
>>/home/lefever/work/install/bin/llc[0x861cada]
>>/home/lefever/work/install/bin/llc(llvm::ScheduleDAG::Run()+0x94)[0x86a9d6c]
>>/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::ScheduleAndEmitDAG(llvm::SelectionDAG&)+0x73)[0x863e64d]
>>/home/lefever/work/install/bin/llc[0x84edf05]
>>/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::CodeGenAndEmitDAG(llvm::SelectionDAG&)+0x13b)[0x863e7ab]
>>/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::SelectBa...
2007 Sep 05
1
[LLVMdev] Exception Problems
...dule
(this=0x41a25a50) at /Volumes/Gir/devel/llvm/llvm.src/lib/CodeGen/
SelectionDAG/ScheduleDAGRRList.cpp:113
#10 0x007c2a6a in llvm::ScheduleDAG::Run (this=0x41a25a50) at /
Volumes/Gir/devel/llvm/llvm.src/lib/CodeGen/SelectionDAG/
ScheduleDAG.cpp:834
#11 0x007f820e in llvm::SelectionDAGISel::ScheduleAndEmitDAG
(this=0x42025600, DAG=@0xbfffe47c) at /Volumes/Gir/devel/llvm/
llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:4847
#12 0x0067fcca in (anonymous
namespace)::X86DAGToDAGISel::InstructionSelectBasicBlock
(this=0x42025600, DAG=@0xbfffe47c) at /Volumes/Gir/devel/llvm/
llvm.src/lib/Target...
2007 Apr 06
0
[LLVMdev] llc assertion failure
...fever/work/install/bin/llc(llvm::ScheduleDAG::EmitSchedule()+0x283)[0x86abf7d]
> >>/home/lefever/work/install/bin/llc[0x861cada]
> >>/home/lefever/work/install/bin/llc(llvm::ScheduleDAG::Run()+0x94)[0x86a9d6c]
> >>/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::ScheduleAndEmitDAG(llvm::SelectionDAG&)+0x73)[0x863e64d]
> >>/home/lefever/work/install/bin/llc[0x84edf05]
> >>/home/lefever/work/install/bin/llc(llvm::SelectionDAGISel::CodeGenAndEmitDAG(llvm::SelectionDAG&)+0x13b)[0x863e7ab]
> >>/home/lefever/work/install/bin/llc(llvm::SelectionDA...
2007 Sep 30
2
[LLVMdev] Q about instruction pattern matching
...n as to how this custom DR->AR op replacer pass fits
> into this whole soup and where it is supposed to happen, as I'm still
> pretty clueless with llvm internals. :)
It should happen right after selection and before scheduling (i.e. in
InstructionSelectionBasicBlock before it calls ScheduleAndEmitDAG). I
would suggest you focusing on getting this down before you start
worrying about the downstream passes.
Evan
>
>
> Thanks,
> Andreas
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.ed...
2007 Sep 29
0
[LLVMdev] Q about instruction pattern matching
On 9/25/07, Evan Cheng <evan.cheng at apple.com> wrote:
> > Hi Evan,
> > wouldn't this generate fairly terrible code if each address register
> > use has to be preceded by instructions to make an address register
> > hold the right value?
>
> No. I would suggest doing this as a instruction selection post pass.
> It would operate on DAGs so you still get
2007 Sep 25
2
[LLVMdev] Q about instruction pattern matching
On Sep 24, 2007, at 1:12 AM, Andreas Fredriksson wrote:
> On 9/24/07, Evan Cheng <evan.cheng at apple.com> wrote:
>
>> I am going to suggest something shocking. :) Since you will end up
>> writing a
>> bunch of target specific code anyway, you might a well write a target
>> specific pass that change generic instructions into data register
>> variant