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Hi all, The goal of this RFC is to make information related to variant scheduling classes accessible at MC level. This would help tools like llvm-mca understand/resolve variant scheduling classes. To achieve this goal, I plan to introduce a new class of scheduling predicates named MCSchedPredicate. An MCSchedPredicate allows the definition of boolean expressions with a well-known semantic, that can be used to generate code for both MachineInstr and MCInst. The new predicates are designed to be completely optional. Scheduling models can use a combination of SchedPredicate and MCSchedPredicat...

...on decompiling tools. > > - Matthias Unfortunately targets have historically been building hooks into TargetInstrInfo. To be clear then, resolveSchedClass should be moved from TargetSchedModel into MCSchedModel (which is where I originally wanted it). Any TargetInstrInfo APIs called from SchedPredicate should be moved to MCInstrInfo, which should be straightforward but annoying. I just looked at the x86 target, and I’m surprised that none of the in tree x86 machine models are using SchedPredicate, so this isn't really a limitation for the current incarnation of the MCA tool. -Andy --------...

...is issued to a four-cycle latency pipeline called LDST. Three cycles after issue, the LDST pipeline wakes up the FPQ micro-op, which writes the result of the load back to the register file. Is it possible to use other instructions already scheduled for the same cycle as part of the evaluation of a SchedPredicate in a SchedVariant? I've got a class of instructions (mostly simple addition) that can dispatch to two different reservation stations (ALQ and AGQ), both of which have a suitable pipeline with the same latency. The dispatch stage can dispatch two instructions per cycle. When it has one instructi...

...atthias > > > Unfortunately targets have historically been building hooks into > TargetInstrInfo. > > To be clear then, resolveSchedClass should be moved from TargetSchedModel > into MCSchedModel (which is where I originally wanted it). Any > TargetInstrInfo APIs called from SchedPredicate should be moved to > MCInstrInfo, which should be straightforward but annoying. > Personally, I don't have a strong opinion on this. My major concern is that not all predicates can be easily rewritten/adapted to work with MCInst and MCschedModel. Predicates can potentially access inform...

> On Mar 5, 2018, at 6:14 PM, Andrew Trick via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > >> On Mar 5, 2018, at 3:38 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> When Ahmed and I worked on the decompiler, we first targeted MC. Going to MI was more difficult and really wouldn’t have gotten us a

...plit instructions. The wakeup signal used to wakeup the second micro-op seems to be a demand that the micro-op issues in that cycle rather than permission to issue when it's convenient. Is it possible to use other instructions already scheduled for the same cycle as part of the evaluation of a SchedPredicate in a SchedVariant? I've got a class of instructions (mostly simple addition) that can dispatch to two different reservation stations (ALQ and AGQ), both of which have a suitable pipeline with the same latency. The dispatch stage can dispatch two instructions per cycle. When it has one instructi...

> On Mar 6, 2018, at 4:20 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > To be clear then, resolveSchedClass should be moved from TargetSchedModel into MCSchedModel (which is where I originally wanted it). Any TargetInstrInfo APIs called from SchedPredicate should be moved to MCInstrInfo, which should be straightforward but annoying. > > Personally, I don't have a strong opinion on this. > My major concern is that not all predicates can be easily rewritten/adapted to work with MCInst and MCschedModel. > > Predicates can potentiall...

...e goal of this RFC is to make information related to variant scheduling > classes accessible at MC level. This would help tools like llvm-mca > understand/resolve variant scheduling classes. > > To achieve this goal, I plan to introduce a new class of scheduling predicates > named MCSchedPredicate. An MCSchedPredicate allows the definition of boolean > expressions with a well-known semantic, that can be used to generate code for > both MachineInstr and MCInst. > > The new predicates are designed to be completely optional. Scheduling models > can use a combination of SchedPred...