Displaying 5 results from an estimated 5 matches for "schedclass".
2017 Sep 22
2
SchedClasses
...rInfo.inc"
int main(int argc, char **argv) {
llvm::MCInstrInfo II;
llvm::InitAArch64MCInstrInfo(&II);
llvm::StringRef ref = II.getName(llvm::AArch64::LDADDALX);
llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX);
printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass);
printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d.SchedClass)->NumMicroOps);
return 0;
}
/*
LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum
*/
2017 Sep 29
0
SchedClasses
...char **argv) {
> llvm::MCInstrInfo II;
>
> llvm::InitAArch64MCInstrInfo(&II);
>
> llvm::StringRef ref = II.getName(llvm::AArch64::LDADDALX);
> llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX);
>
> printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass);
>
> printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d.SchedClass)->NumMicroOps);
>
> return 0;
> }
>
> /*
> LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum
> */
I bet the problem is that “WriteAtomic” is marked unsupported...
2017 Sep 30
1
SchedClasses
...strInfo II;
> >
> > llvm::InitAArch64MCInstrInfo(&II);
> >
> > llvm::StringRef ref = II.getName(llvm::AArch64::LDADDALX);
> > llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX);
> >
> > printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass);
> >
> > printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d.
> SchedClass)->NumMicroOps);
> >
> > return 0;
> > }
> >
> > /*
> > LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum
> > */
>
> I be...
2018 May 10
2
[RFC] MC support for variant scheduling classes.
...ve a "portable"
semantic. A predicate is essentially an opaque block of code, and the
semantic of predicates is unknown to tablegen. Tablegen can only trust the
user, and just "copy-paste" code blocks from the various predicates to an
auto-generated `XXXGenSubtargetInfo::resolveSchedClass()` function.
This limits our ability to reason on predicates. In particular, it makes it
extremely hard (if not impossible) for tools that can only access the MC
layer
to reuse predicate definitions to resolve variant scheduling classes.
If instead we expose the semantic of predicates to tablegen...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...ne assembly
>> + if (MI->isInlineAsm())
>> + return false;
>> +
>> + // We check if MI has any functional units mapped to it.
>> + // If it doesn't, we ignore the instruction.
>> + const MCInstrDesc& TID = MI->getDesc();
>> + unsigned SchedClass = TID.getSchedClass();
>> + const InstrStage* IS = ResourceTracker->getInstrItins()->beginStage(SchedClass);
>> + unsigned FuncUnits = IS->getUnits();
>> + return !FuncUnits;
>> +}
>> +
>> +// isSoloInstruction: - Returns true for instructions that mu...