search for: schedalias

Hi, I am having some trouble understanding the scheduling scheme for the C-A9. Looking at the ARMScheduleA9.td file I find this line that overrides the target SchedWrite with processor specific latencies. def : SchedAlias<WriteALU, A9WriteALU>; However, in this same file, I find the lines presented below, which are mapping the SchedReadWrite to, for example, the ANDri instruction. // ===---------------------------------------------------------------------===// // Subtarget-specific overrides. Map opcodes to...

...like this: > > def : WriteRes<WriteShift, [IEC_RSV0]> { let Latency = 2; } > > Maybe a new WriteShiftCL type should be added to X86Schedule.td and referenced in X86InstrShiftRotate.td. Then SLM can define it with Latency = 4, and X86SchedSandyBridge.td can have: > > def : SchedAlias<WriteShiftCL, WriteShift>; > > It's also possible for a subtarget to override specific operations by pattern matching opcodes without complicating the architecture definitions files. > > > -Andy

Ping From: Mandeep Singh Grang [mailto:mgrang at codeaurora.org] Sent: Tuesday, February 03, 2015 4:34 PM To: 'llvmdev at cs.uiuc.edu' Cc: 'ghoflehner at apple.com'; 'apazos at codeaurora.org'; mgrang at codeaurora.org Subject: Question on Machine Combiner Pass Hi, In the file lib/CodeGen/MachineCombiner.cpp I see that in the function