Displaying 2 results from an estimated 2 matches for "scevmulexpr".
2019 Jun 25
2
SCEVExpander bug?
Hi,
We have recently encountered incorrect code generation issues and I think it is a SCEVExpander bug exposed by a recent patch to add nuw/nsw flags when generating code for SCEVMulExpr.
The test case IR looks like this-
%1 = load i16, i16* %arrayidx
%2 = and i16 %1, -32768
The SCEV form of %2 is this-
(-32768 * (%1 /u -32768))<nuw><nsw>
It has both nsw/nuw flags. The signed range of the second operand of SCEVMulExpr (%1 /u -32768) is [0, 2). So it can be either 0...
2016 Jun 02
6
-Wmisleading-indentation violations
...ard... [-Wmisleading-indentation]
if (!isa<SCEVUnknown>(Reg) &&
^~
/home/dsl11/dev/llvm-upstream/src/lib/Transforms/Scalar/LoopStrengthReduce.cpp:950:5:
note: ...this statement, but the latter is misleadingly
indented as if it is guarded by the ‘if’
NumIVMuls += isa<SCEVMulExpr>(Reg) &&
^~~~~~~~~
```
and
```
/home/dsl11/dev/llvm-upstream/src/lib/Target/AMDGPU/R600MachineScheduler.cpp:
In member function ‘llvm::R600SchedStrategy::AluKind llvm::R600S
chedStrategy::getAluKind(llvm::SUnit*) const’:
/home/dsl11/dev/llvm-upstream/src/lib/Target/AMDGPU/R600...