search for: scavang

Chris Lattner wrote: >> and then have 'virtual_register' allocated on next iteration of register >> allocator? > > This is one approach. Another approach is to have to spiller scavange > registers, which is the subject of this enhancement request: > http://llvm.org/PR768 Can you given some references for this "scavange" thing? Google and ResearchIndex are silent on the topic. >> Also, while RegAllocLocal and RegAllocSimple directly call >> storeRegT...

...e implementation can then create code like: > > virtual_register = frame_pointer + offset > [virtual_register] > > and then have 'virtual_register' allocated on next iteration of register > allocator? This is one approach. Another approach is to have to spiller scavange registers, which is the subject of this enhancement request: http://llvm.org/PR768 > Also, while RegAllocLocal and RegAllocSimple directly call > storeRegToStackSlot, I would not found any calls to that method in > RegAllocLinearScan. Am I missing something? RegAllocLinearScan just do...

Hi, right now, LLVM does register spilling by: 1. Creating stack object 2. Passing index of that stack object to MRegisterInfo::storeRegToStackSlot 3. At later stage, frame indices are replaced by calling to MRegisterInfo::eliminateFrameIndex. This works for me, but there's slight problem. The target does not have "register + contant" addressing mode, so accessing frame index

...functions to do "generalized" boxplots sometime ago (e.g., "vase" or "violin, "diamond" plots, etc). There's code to draw these gboxplots at arbitrary positions. Please take a look at the help below and let me know if you'd like either to port it R or scavange some of the code. David A James Phone: (908) 582-3082 Bell Labs, Lucent Technologies Fax: (908) 582-3340 600 Mountain Ave Email: dj at bell-labs.com Murray Hill, NJ 07974 -------------------------------------------------------------------- Genera...

Hello LLVM, The ARM target sometimes adds an instruction with a virtual register in eliminateFrameIndex(): https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp This looks late for a virtual register to appear. Where is this vreg made real? Thanks, -steve