search for: scaled_bits

Displaying 3 results from an estimated 3 matches for "scaled_bits".

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2018 Jun 05
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...need constant integer values or would a ConstantExpr > sufffice? We could add a ConstantVScale or something to make it work. I agree the name is not ideal and I'm open to suggestions -- I was thinking of the two integers representing the known-at-compile-time terms in an expression: '(scaled_bits * vscale) + unscaled_bits'. Assuming the pair is of the form (unscaled, scaled), then for a type with a size known at compile time like <4 x i32> the size would be (128, 0). For a scalable type like <scalable 4 x i32> the size would be (0, 128). For a struct with, say, a <scal...
2018 Jun 06
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...stantExpr >>> sufffice? We could add a ConstantVScale or something to make it work. >> >> I agree the name is not ideal and I'm open to suggestions -- I was thinking of the two >> integers representing the known-at-compile-time terms in an expression: >> '(scaled_bits * vscale) + unscaled_bits'. >> >> Assuming the pair is of the form (unscaled, scaled), then for a type with a size known at >> compile time like <4 x i32> the size would be (128, 0). >> >> For a scalable type like <scalable 4 x i32> the size would be...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi, Now that Sander has committed enough MC support for SVE, here's an updated RFC for variable length vector support with a set of 14 patches (listed at the end) to demonstrate code generation for SVE using the extensions proposed in the RFC. I have some ideas about how to support RISC-V's upcoming extension alongside SVE; I'll send an email with some additional comments on