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0x0f 0x6f 0xc8 And 0x0f 0x7f 0xc1 Should both be movq % mm0, % mm1. (AT&T) However, llvm 3.4 at least does not recognise the second variant as being a valid instruction. We are currently compiling up latest src incase it has been fixed. If not, could someone take a look or recommend how to fix? Lee -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, While working some more on the backend, I've added callee register saving and have come across something odd (I assume its because i've not implemented something), this is with optimisations which makes it even more odd : MOV.L [R7+ 12], R1 ; 4-byte Folded Spill MOV.L [R7+ 8], R2 ; 4-byte Folded Spill ADD.L R0,R0 + R1 ADD.L

Hi, I've been experimenting with writing a backend for LLVM (3.2) (having already written a frontend http://savourysnax.github.com/EDL), everything was going reasonably ok ( calls/returns, epilogue, prologue, etc are all working), up until I tried to place support for conditional branches. Given this simple program : int test(int c,int d) { if (c) { return

Recently I have been deeply troubled by evidence revealing the degree to which U.S. based corporations (well actually all resident in any of the so-called 5-eyes countries) appear to have rolled over and assumed the position with respect to NSA inspired pressure to cripple public key encryption and facilitate intrusions into their software products. This has engendered in me a significant degree

Hi, While working on adding newlib to my backend I hit the following assert : Assertion failed: BestRC && "Couldn't find the register class", file TargetRegisterInfo.cpp, line 112 The following llvm causes this : define void @specialBreak(i8* %out) nounwind { entry: %out.addr = alloca i8*, align 4 store i8* %out, i8** %out.addr, align 4 %0 = load i8** %out.addr,