Displaying 11 results from an estimated 11 matches for "saulais".
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2018 Nov 15
2
Per-write cycle count with ReadAdvance - Do I really need that?
...ith current tblgen implement.
Can you comment and help?
--
Garfee Guan,
LLVM Compiler Backend Engineer
Enflame Technology Co.
Website: http://www.enflame-tech.com/
--------------------------------------------------------------------
[llvm-dev] Per-write cycle count with ReadAdvance
*Pierre-Andre Saulais via llvm-dev* llvm-dev at lists.llvm.org
<llvm-dev%40lists.llvm.org?Subject=Re%3A%20%5Bllvm-dev%5D%20Per-write%20cycle%20count%20with%20ReadAdvance&In-Reply-To=%3C565C3F99.9060206%40codeplay.com%3E>
*Mon Nov 30 04:22:49 PST 2015*
- Previous message: [llvm-dev] difference with autotoo...
2015 Sep 28
3
Parse Instruction
Hi ES,
From what I understand instruction parsing is divided into two parts:
- Parsing an operand list (XXXAsmParser::ParseInstruction)
- Turning the operand list into an actual instruction
(XXXAsmParser::MatchAndEmitInstruction)
The second part does the validation (e.g. how many operands, what kind,
etc) while the first part only does the parsing. That's why I think in
the first part
2017 Jan 27
2
Preserving Call to Intrinsic function
Hello everyone,
Consider we have this following set of code:
int foo() {
int a,b;
a = __builtin_XX(0x11);
b = __builtin_XX(0x11);
return a+b;
}
The problem currently is that LLVM eliminated the second call and copied
the result from the first call into a new set of registers. Is there is a
way to force LLVM to generate two explicit calls to a builtin function. The
builtin takes in an integer
2018 Nov 17
2
Per-write cycle count with ReadAdvance - Do I really need that?
...t; -Andy
>
> --
> Garfee Guan,
> LLVM Compiler Backend Engineer
> Enflame Technology Co.
> Website: http://www.enflame-tech.com/
>
> --------------------------------------------------------------------
> [llvm-dev] Per-write cycle count with ReadAdvance
> *Pierre-Andre Saulais via llvm-dev* llvm-dev at lists.llvm.org
> <llvm-dev%40lists.llvm.org?Subject=Re%3A%20%5Bllvm-dev%5D%20Per-write%20cycle%20count%20with%20ReadAdvance&In-Reply-To=%3C565C3F99.9060206%40codeplay.com%3E>
> *Mon Nov 30 04:22:49 PST 2015*
>
>
> - Previous message: [llvm-dev]...
2018 Nov 19
2
Per-write cycle count with ReadAdvance - Do I really need that?
...arfee Guan,
>> LLVM Compiler Backend Engineer
>> Enflame Technology Co.
>> Website: http://www.enflame-tech.com/
>>
>> --------------------------------------------------------------------
>> [llvm-dev] Per-write cycle count with ReadAdvance
>> *Pierre-Andre Saulais via llvm-dev* llvm-dev at lists.llvm.org
>> <llvm-dev%40lists.llvm.org?Subject=Re%3A%20%5Bllvm-dev%5D%20Per-write%20cycle%20count%20with%20ReadAdvance&In-Reply-To=%3C565C3F99.9060206%40codeplay.com%3E>
>> *Mon Nov 30 04:22:49 PST 2015*
>>
>>
>> - Previous...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote:
>
> On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote:
>
>>
>> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote:
>>
>>> Hi Andrew,
>>>
>>> We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models.
>>>
>&...
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote:
> Hi Andrew,
>
> We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models.
>
> To expand on what JinGu mentioned, our ta...
2015 Dec 04
2
InstrStage, Interpretation of getUnits()
Here is the code
<https://github.com/llvm-mirror/llvm/blob/c68dcdb413079d92118839dbd835e125293f411a/include/llvm/MC/MCInstrItineraries.h#L75>
for InstrStage::getUnits()
/// \brief Returns the choice of FUs.
unsigned getUnits() const { return Units_; }
This method returns an integer. How does one interpret it? As far as I see
it it should tell me what resources are used by a given stage but
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote:
> Hi Andy,
>
> I am trying to schedule and packetize instructions for VLIW at post-RA
> stage or final codegen stage, where code transformations are not allowed
> any more, because hardware can not resolve resource conflict. There is a
> simple example as following:
>
> ADD dest_reg1, src_reg1,
2020 Mar 12
3
Getting up to speed with llvm backends. Machine Instruction operands.
...mmer with no LLVM backend experience evaluating
llvm for creating a Hitachi 6309 backend.
This post is about finding out more about machine instruction operands.
The documentation I have read so far includes:
- the online manuals
- Building an LLVM Backend. Fraser Cormack Pierre-André Saulais
- The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend. Connor
Jan Goldberg
- Design and Implementation of a TriCore Backend for the LLVM Compiler
Framework. Christoph Erhardt
I have also cloned llvm 9.0.1 and started looking at some of the targets. A
little overwhelming!
At...
2014 Dec 21
3
[LLVMdev] Indexed Load and Store Intrinsics - proposal
On 12/18/2014 11:56 AM, dag at cray.com wrote:
> "Demikhovsky, Elena" <elena.demikhovsky at intel.com> writes:
>
>> Semantics:
>> For i=0,1,…,N-1: if (Mask[i]) {*(BaseAddr + VectorOfIndices[i]*Scale)
>> = VectorValue[i];}
>> VectorValue: any float or integer vector type.
>> BaseAddr: a pointer; may be zero if full address is placed in the