search for: sardask01

Displaying 20 results from an estimated 39 matches for "sardask01".

2014 Dec 11
2
[LLVMdev] Phabricator update
Hi Manuel, Thanks for the help. Still persists for me too. Instead of waiting indefinitely, now I get this error: Unhandled Exception ("AphrontDeadlockQueryException") #1205: Lock wait timeout exceeded; try restarting transaction On Thu, Dec 11, 2014 at 11:26 AM, suyog sarda <sardask01 at gmail.com> wrote: > The problem still persist :( > > On 12/11/14, Manuel Klimek <klimek at google.com> wrote: >> Another php type problem; can you please try again. Thanks! >> >> On Thu Dec 11 2014 at 1:37:32 PM Bruno Cardoso Lopes < >> bruno.cardoso...
2015 May 04
3
[LLVMdev] AVX2 Cost Table in X86TargetTransformInfo
...ing and cost of these operations are taken from BaseTTI (which is generic). IMO, it will make things more clear. Your thoughts on this?? Regards, Suyog Sarda On 4 May 2015 21:57, "Nadav Rotem" <nrotem at apple.com> wrote: > > > On May 4, 2015, at 2:36 AM, suyog sarda <sardask01 at gmail.com> wrote: > > > > Hi all, > > > > I have a query regarding Cost Table for AVX2 in TargetTransformInfo. > > > > The table consist of entries for shift and div operations only. There > are no entries for ADD, SUB and MUL for AVX2 cost table. Those...
2014 Dec 11
2
[LLVMdev] Phabricator update
Another php type problem; can you please try again. Thanks! On Thu Dec 11 2014 at 1:37:32 PM Bruno Cardoso Lopes < bruno.cardoso at gmail.com> wrote: > I'm facing the same problem. > > On Thu, Dec 11, 2014 at 10:16 AM, suyog sarda <sardask01 at gmail.com> wrote: > > Hi, > > I am facing problem while submitting patch on phab. All things go smooth > - > > create diff, create revision, specify title and comments. However, when > I > > try to submit the diff by clicking "save" button, it takes a...
2014 Dec 11
2
[LLVMdev] Phabricator update
...gt;>> >>> On 12/10/14 1:59 PM, Manuel Klimek wrote: >>>> >>>> Phab is back up - it's still a little slow (the mysql database we use is >>>> doing some cleanups). >>>> >>>> On Wed Dec 10 2014 at 5:07:07 PM suyog sarda <sardask01 at gmail.com> wrote: >>>> >>>>> And i was thinking something wrong with my proxy configuration :P >>>>> >>>>> On Wed, Dec 10, 2014 at 6:47 PM, Manuel Klimek <klimek at google.com> wrote: >>>>> >>>>>>...
2014 Dec 10
2
[LLVMdev] Phabricator update
Phab is back up - it's still a little slow (the mysql database we use is doing some cleanups). On Wed Dec 10 2014 at 5:07:07 PM suyog sarda <sardask01 at gmail.com> wrote: > And i was thinking something wrong with my proxy configuration :P > > On Wed, Dec 10, 2014 at 6:47 PM, Manuel Klimek <klimek at google.com> wrote: > >> Heya, >> >> if you wonder why phabricator is down - it's an upgrade that is runn...
2014 Dec 11
3
[LLVMdev] [cfe-dev] Phabricator update
...t; >>> >>> On 12/10/14 1:59 PM, Manuel Klimek wrote: >>> >>>> Phab is back up - it's still a little slow (the mysql database we use is >>>> doing some cleanups). >>>> >>>> On Wed Dec 10 2014 at 5:07:07 PM suyog sarda <sardask01 at gmail.com> >>>> wrote: >>>> >>>> And i was thinking something wrong with my proxy configuration :P >>>>> >>>>> On Wed, Dec 10, 2014 at 6:47 PM, Manuel Klimek <klimek at google.com> >>>>> wrote: >>&gt...
2014 Dec 11
3
[LLVMdev] [cfe-dev] Phabricator update
...very helpful. > > > Cheers, > > Jon > > > On 12/10/14 1:59 PM, Manuel Klimek wrote: > >> Phab is back up - it's still a little slow (the mysql database we use is >> doing some cleanups). >> >> On Wed Dec 10 2014 at 5:07:07 PM suyog sarda <sardask01 at gmail.com> wrote: >> >> And i was thinking something wrong with my proxy configuration :P >>> >>> On Wed, Dec 10, 2014 at 6:47 PM, Manuel Klimek <klimek at google.com> >>> wrote: >>> >>> Heya, >>>> >>>> i...
2015 Apr 10
2
[LLVMdev] MMX/SSE subtarget feature in IR
...on't know whether work has been done to specifically do something special for this combination, since use of MMX overlaps with X87 floating point state. The processors that support mmx, but not SSE would be Pentium w MMX processor Pentium II family processors Kevin From: suyog sarda [mailto:sardask01 at gmail.com] Sent: Friday, April 10, 2015 2:51 AM To: Smith, Kevin B Cc: Sanjay Patel; David Majnemer; LLVM Developers Mailing List Subject: Re: [LLVMdev] MMX/SSE subtarget feature in IR Hi Kevin, I had another query for 32 bit x86. (Apology for being naive) I guess the default CPU on 32-bit x8...
2014 Nov 10
2
[LLVMdev] [Vectorization] Mis match in code generated
...> > > Comments/Suggestions are most welcomed. > > > > > > Regards, > > > > Suyog > > > > > > > > > > > > > > > > > > > > > > > > > > On Sat, Sep 20, 2014 at 12:05 AM, suyog sarda <sardask01 at gmail.com < > sardask01 at gmail.com>> wrote: > > > > > Hi Arnold, > > > > > > > > > Thanks for your reply. > > > > > > > > > I tried test case as suggested by you. > > > > > > void foo(int *a, int...
2015 May 04
2
[LLVMdev] AVX2 Cost Table in X86TargetTransformInfo
Hi all, I have a query regarding Cost Table for AVX2 in TargetTransformInfo. The table consist of entries for shift and div operations only. There are no entries for ADD, SUB and MUL for AVX2 cost table. Those entries are present in Cost Table for AVX. The reason for query is - when my sub target feature is AVX2, in SLP Vectorization, while calculating scalar cost of ADD, it doesn't see
2014 Aug 13
2
[LLVMdev] Efficient Pattern matching in Instruction Combine
...an implement it for generic boolean expression minimization. Regards, Suyog On Wed, Aug 13, 2014 at 2:30 AM, Sean Silva <chisophugis at gmail.com> wrote: > Re-adding the mailing list (remember to hit "reply all") > > > On Tue, Aug 12, 2014 at 9:36 AM, suyog sarda <sardask01 at gmail.com> wrote: > >> Thanks Sean for the reply. >> >> >> On Mon, Aug 11, 2014 at 11:49 PM, Sean Silva <chisophugis at gmail.com> >> wrote: >> >>> >>> >>> >>> On Fri, Aug 8, 2014 at 1:34 PM, suyog sarda <sard...
2014 Dec 11
2
[LLVMdev] [cfe-dev] Phabricator update
...l > > > > > > > > Cheers, > > Jon > > > > On 12/10/14 1:59 PM, Manuel Klimek wrote: > > Phab is back up - it's still a little slow (the mysql database we use is > doing some cleanups). > > On Wed Dec 10 2014 at 5:07:07 PM suyog sarda <sardask01 at gmail.com> wrote: > > And i was thinking something wrong with my proxy configuration :P > > On Wed, Dec 10, 2014 at 6:47 PM, Manuel Klimek <klimek at google.com> wrote: > > Heya, > > if you wonder why phabricator is down - it's an upgrade that is running a &g...
2013 Dec 19
0
[LLVMdev] LLVM ARM VMLA instruction
On 19 December 2013 08:50, suyog sarda <sardask01 at gmail.com> wrote: > It may seem that total number of cycles are more or less same for single > vmla and vmul+vadd. However, when vmul+vadd combination is used instead of > vmla, then intermediate results will be generated which needs to be stored > in memory for future access. Th...
2014 Aug 07
4
[LLVMdev] Efficient Pattern matching in Instruction Combine
Hi, All, Duncan, Rafael, David, Nick. This is regarding pattern matching in InstructionCombine pass. We use 'match' functions many times, but it doesn't do the pattern matching effectively. e.x. Lets take pattern : (A ^ B) | ((B ^ C) ^ A) -> (A ^ B) | C (B ^ A) | ((B ^ C) ^ A) -> (A ^ B) | C Both the patterns above are same, since ^ is commutative in Op0. But,
2014 Sep 19
3
[LLVMdev] [Vectorization] Mis match in code generated
...gt; *F(int *sum ...){*sum = > a[0]+a[1]+a[2]+a[3]+a[4]+a[5]+a[6]+a[7]+a[8]+a[9]+a[10]+a[11]+a[12]+a[13]+a[14]+a[15];}* > > If it works we would only need to look for horizontal reductions at > returns. > > Sent from my iPhone > > On Sep 18, 2014, at 12:24 PM, suyog sarda <sardask01 at gmail.com> wrote: > > Hi Nadav, > > Thanks for the quick reply !! > > Ok, so as of now we are lacking capability to handle flat large reductions. > > I did go through function vectorizeChainsInBlock() (line number 2862). In > this function, > we try to vectorize...
2015 May 04
2
[LLVMdev] Modifying LoopUnrollingPass
Optimization passes running before LoopVectorizer should be able to combine the two statements (this should be happening in O1. Pls check) arr[i] = a + i sum += arr[i] to sum += a + i Not sure, why are you using the array there. - Suyog On 4 May 2015 23:11, "Michael Zolotukhin" <mzolotukhin at apple.com> wrote: > Hi Yaduveer, > > Vectorizer probably fails because it
2014 Aug 13
2
[LLVMdev] Efficient Pattern matching in Instruction Combine
...g file that makes any of the non-trivial transforms easy to miss in the noise. On Tue, Aug 12, 2014 at 2:00 PM, Sean Silva <chisophugis at gmail.com> wrote: > Re-adding the mailing list (remember to hit "reply all") > > > On Tue, Aug 12, 2014 at 9:36 AM, suyog sarda <sardask01 at gmail.com> wrote: >> >> Thanks Sean for the reply. >> >> >> On Mon, Aug 11, 2014 at 11:49 PM, Sean Silva <chisophugis at gmail.com> >> wrote: >>> >>> >>> >>> >>> On Fri, Aug 8, 2014 at 1:34 PM, suyog sarda...
2014 Aug 08
4
[LLVMdev] Efficient Pattern matching in Instruction Combine
Hi Duncan, David, Sean. Thanks for your reply. > It'd be interesting if you could find a design that also treated these > the same: > > (B ^ A) | ((A ^ B) ^ C) -> (A ^ B) | C > (B ^ A) | ((B ^ C) ^ A) -> (A ^ B) | C > (B ^ A) | ((C ^ A) ^ B) -> (A ^ B) | C > > I.e., `^` is also associative. Agree with Duncan on including associative operation too.
2013 Dec 19
2
[LLVMdev] LLVM ARM VMLA instruction
On Thu, Dec 19, 2013 at 4:36 PM, Renato Golin <renato.golin at linaro.org>wrote: > On 19 December 2013 08:50, suyog sarda <sardask01 at gmail.com> wrote: > >> It may seem that total number of cycles are more or less same for single >> vmla and vmul+vadd. However, when vmul+vadd combination is used instead of >> vmla, then intermediate results will be generated which needs to be stored >> in memory f...
2013 Dec 19
4
[LLVMdev] LLVM ARM VMLA instruction
Hi Tim, > > cortex-a15 vfpv4 : vmla instruction emitted (which is a NEON instruction) > > I get a VFP vmla here rather than a NEON one (clang -target > armv7-linux-gnueabihf -mcpu=cortex-a15): "vmla.f32 s0, s1, s2". Are > you seeing something different? > As per Renato comment above, vmla instruction is NEON instruction while vmfa is VFP instruction. Correct