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Hi, I'm working on support for the latest generation of AMD GPUs (Southern Islands) in the R600 backend, and I need some advice on how to handle interactions between two different ALUs. The processors on Southern Islands GPUs are grouped into compute units, which contain 1 Scalar ALU (sALU) and 64 Vector ALUs (vALU). The sALU is mainly responsible for flow control (implemented using predicates) and loading data from read-only memory. The vALU does most of the data processing and has a much larger instruction set than the sALU. Even though a compute unit has 1 sALU and 64 vALUs, fr...

...ns or registers. > We also have a somewhat related issue with newer GPUs, that have essentially two different instruction sets. However, instead of having one for pointers and one for integers like your target, we have a Vector ALU (VALU) for manipulating integers and floats and a Scalar ALU (SALU) for handling control flow and loading for constant memory. There is a lot overlap between these two instruction sets (i.e both support almost all standard integer operations). Since tablegen matches patterns based on types, it is impossible for us to select from both instruction sets, and it sou...

Hi, In our version of LLVM, we've added different-sized iPTR* types, so we have an iPTR256 for our fat pointers. This causes some problems with constraints, because the way that TableGen resolves constraints is not expected to handle multiple pointer types. We've added a flag that can be set on a per-backend basis to turn this off. Our problem is perhaps a bit different form yours,

David, thanks for your immediate response. Since iPTR is a reserved type for tablegen internal use, can you make a further explanation? On the other hand, it can be simply treated as a register class assignment problem during register allocation. Assume both pointer and integet have a 32 bit width. backend handles it just as to i32. When it performs register allocation, it can retrieve from

...// /*plain 32-bit add*/ {&PartialMapping[0], 1}, /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2}, /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1} /// }; This looks almost like the problem I want to solve for AMDGPU. There are 2 main register banks. On the SALU, some 64-bit operation are available which can only be 32-bit on the VALU. For example, if all of the input operands aren’t in the scalar bank, a 64-bit and needs to be split into 2 32-bit ands. It’s illegal to copy from the vector to the scalar bank, since these don’t mean what vector and scalar m...