Displaying 3 results from an estimated 3 matches for "saddv".
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2016 Nov 26
9
[RFC] Supporting ARM's SVE in LLVM
...pletely refactoring core LLVM passes without a clue
is a few steps too far.
I'm not asking for a full spec. All I'm asking is for a description of
the intended basic functionality. Addressing modes, how to extract
information from unknown lanes, or if all reduction steps will be done
like `saddv`. Without that information, I cannot know what is the best
IR representation for scalable vectors or what will be the semantics
of shufffle / extract / insert operations.
> "complex constant" is the term used within the LangRef. Although its value can be different across certain int...
2016 Nov 27
4
[RFC] Supporting ARM's SVE in LLVM
...ue
> is a few steps too far.
>
> I'm not asking for a full spec. All I'm asking is for a description of
> the intended basic functionality. Addressing modes, how to extract
> information from unknown lanes, or if all reduction steps will be done
> like `saddv`. Without that information, I cannot know what is the best
> IR representation for scalable vectors or what will be the semantics
> of shufffle / extract / insert operations.
>
>
> > "complex constant" is the term used within the LangRef. Although its value...
2016 Nov 25
2
[RFC] Supporting ARM's SVE in LLVM
Hi Graham,
I'll look into the patches next, but first some questions after
reading the available white papers on the net.
On 24 November 2016 at 15:39, Graham Hunter <Graham.Hunter at arm.com> wrote:
> This complex constant represents the runtime value of `n` for any scalable type
> `<n x m x ty>`. This is primarily used to increment induction variables and
> generate