Displaying 4 results from an estimated 4 matches for "s_br".
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2007 Apr 23
4
[LLVMdev] Instruction pattern type inference problem
...insights?
For instance:
where GPRegs contains types [i32, f32]
def BEQ : IF8<Opc.BEQ,
(ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
"beq $Rsrc1, $Rsrc2, $SImm16",
[(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
$SImm16)], s_br>;
Tablegen reports:
BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2,
SETEQ:Other), (bb:Other):$SImm16)
as soon as I add a register class that supports either [v2i32] or
[v4i32] I get the following:
BGE: (brcond:void (setcc:isInt GPRegs:i32:$Rsrc1, 0:i32,
SETGE:Ot...
2007 Apr 23
0
[LLVMdev] Instruction pattern type inference problem
...gt; where GPRegs contains types [i32, f32]
>
> def BEQ : IF8<Opc.BEQ,
> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
> "beq $Rsrc1, $Rsrc2, $SImm16",
> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
> $SImm16)], s_br>;
>
> Tablegen reports:
> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2,
> SETEQ:Other), (bb:Other):$SImm16)
>
> as soon as I add a register class that supports either [v2i32] or
> [v4i32] I get the following:
>
> BGE: (brcond:void (setcc:isIn...
2007 Apr 23
1
[LLVMdev] Instruction pattern type inference problem
...s types [i32, f32]
>>
>> def BEQ : IF8<Opc.BEQ,
>> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
>> "beq $Rsrc1, $Rsrc2, $SImm16",
>> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
>> $SImm16)], s_br>;
>>
>> Tablegen reports:
>> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2,
>> SETEQ:Other), (bb:Other):$SImm16)
>>
>> as soon as I add a register class that supports either [v2i32] or
>> [v4i32] I get the following:
>>
>&...
2007 Apr 23
0
[LLVMdev] Instruction pattern type inference problem
...t; where GPRegs contains types [i32, f32]
>
> def BEQ : IF8<Opc.BEQ,
> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
> "beq $Rsrc1, $Rsrc2, $SImm16",
> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
> $SImm16)], s_br>;
>
> Tablegen reports:
> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:
> $Rsrc2, SETEQ:Other), (bb:Other):$SImm16)
>
> as soon as I add a register class that supports either [v2i32] or
> [v4i32] I get the following:
>
> BGE: (brcond:void (setcc:...