search for: s25_d

Displaying 3 results from an estimated 3 matches for "s25_d".

2015 Jul 24
0
[LLVMdev] SIMD for sdiv <2 x i64>
------------------------------------ IR ------------------------------------------------------------------ if.then.i.i.i.i.i.i: ; preds = %if.then4 %S25_D = zext <2 x i32> %splatLDS17_D.splat to <2 x i64> %umul_with_overflow.i.iS26_D = shl <2 x i64> %S25_D, <i64 3, i64 3> %extumul_with_overflow.i.iS26_D = extractelement <2 x i64> %umul_with_overflow.i.iS26_D, i32 1 %call5.i.i = tail call noalias i8* @_Znam(i64 %ext...
2015 Jul 24
1
[LLVMdev] SIMD for sdiv <2 x i64>
...rewritten in terms of the i8* %call5.i.i and a bitcast. On 07/24/2015 10:52 AM, zhi chen wrote: > ------------------------------------ IR > ------------------------------------------------------------------ > if.then.i.i.i.i.i.i: ; preds = %if.then4 > %S25_D = zext <2 x i32> %splatLDS17_D.splat to <2 x i64> > %umul_with_overflow.i.iS26_D = shl <2 x i64> %S25_D, <i64 3, i64 3> > %extumul_with_overflow.i.iS26_D = extractelement <2 x i64> > %umul_with_overflow.i.iS26_D, i32 1 > %call5.i.i = tail call noalia...
2015 Jul 24
2
[LLVMdev] SIMD for sdiv <2 x i64>
On 07/24/2015 03:42 AM, Benjamin Kramer wrote: >> On 24.07.2015, at 08:06, zhi chen <zchenhn at gmail.com> wrote: >> >> It seems that that it's hard to vectorize int64 in LLVM. For example, LLVM 3.4 generates very complicated code for the following IR. I am running on a Haswell processor. Is it because there is no alternative AVX/2 instructions for int64? The same thing