Displaying 2 results from an estimated 2 matches for "s10immpred".
2016 Mar 30
1
infer correct types from the pattern
On 3/30/2016 4:42 PM, Rail Shafigulin via llvm-dev wrote:
> i'm getting a
>
> Could not infer all types in pattern!
>
> error in my backend. it is happening on the following instruction:
>
> VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32}
> VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)).
>
> how do i make it use appropriate types? in other words if it is f32 then
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
>> (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
>> "$dst = or($src1, and($src2, #$src3))",
>> - [(set IntRegs:$dst,
>> - (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],
>> + [(set (i32 IntRegs:$dst),
>> + (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
>> + s10ImmPred:$src3)))],
>> "$src2 = $dst">,
>> Requi...