search for: ryta1203

---------- Forwarded message ---------- From: Ryan Taylor <ryta1203 at gmail.com> Date: Mon, Dec 12, 2011 at 4:58 PM Subject: Re: [LLVMdev] GetElementPtr To: Eli Friedman <eli.friedman at gmail.com> Sorry, So what I'm trying to ask is are the widths given (32, 64) for the index and the offset the widths of the index and offset values or the width...

So in this example: %idx = getelementptr { float*, i32 }* %MyStruct, i64 0, i32 1 Why is it picking i64 for the index but i32 for the offset? On Mon, Dec 12, 2011 at 4:58 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > > ---------- Forwarded message ---------- > From: Ryan Taylor <ryta1203 at gmail.com> > Date: Mon, Dec 12, 2011 at 4:58 PM > Subject: Re: [LLVMdev] GetElementPtr > To: Eli Friedman <eli.friedman at gmail.com> > > > Sorry, > &...

Does a transform exist to breakdown the GEP? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111206/e88dddfe/attachment.html>

Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My q...

...bleUI] Custom widget with id loop-button does not return a valid node Has anyone else run into this issue? (again, this problem does not exist if I revert to 3.4 but I'm not sure it's an llvm issue either, I really don't know) Thanks. On Sat, Aug 1, 2015 at 3:47 PM, Ryan Taylor <ryta1203 at gmail.com<mailto:ryta1203 at gmail.com>> wrote: Ah, I missed that subltety. Thanks. On Aug 1, 2015 2:43 PM, "Mehdi Amini" <mehdi.amini at apple.com<mailto:mehdi.amini at apple.com>> wrote: The diff is not only the && and || but also the leading !: diff -...

AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being generated. On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I have not tried 3.5, it's a significant amount of work to port from one > version to the next though, I did not personally do the 3.4 to 3.6 porting. > I agree though, it was very strange that it suddenly just changed behavior. > > It looks like to...

> On Aug 22, 2015, at 9:10 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > One last question regarding this please. > > Why aren't we simply changing the register class in AddRegisterOperand instead of building a new COPY? I admit I haven't thought this out but for my test cases so far this works just fine and reduces the...

> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I'm trying to do something like this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) >...

...; PTRRegs:%vreg0 RetRA On Tue, Aug 25, 2015 at 3:56 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Oh, could you paste the MIs you get right after ISel (the whole def use > chain of the interesting vregs)? > > Q. > > On Aug 25, 2015, at 12:00 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being > generated. > > On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> > wrote: > >> >> On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta...

...type checking? If we have defined a RegClass for that instruction, it should use that regclass or subregclasses (depending on use/def info), correct? On Tue, Aug 25, 2015 at 1:37 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:29 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > 1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the > multiclass. The IMM in my case is a global. So you can see that > GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst > operands, in this case (MOV16Copy_IMM_REG) it...

...mhx, memhx, [(directStore (dstType (OpNode (srcAType (load addr16:$srcA)))), addr16:$dstD)]>; } defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, i16, i16, simm16, immSExt16x>; On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Quentin, > > 1. I'll take a look, it's also picking the reg class by the > SimpleValueType and then getting the common subclass. Choosing to constrain > the reg class to GPRRegs instead of GPRBaseRegs seems like it could lead to > unintended sp...

...o get the TD defined register class for an operand for a machine instruction. There must be a way since LLVM produces valid registers for the operands. On Tue, Aug 25, 2015 at 1:18 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterClass dstReg, ValueType srcAType, > ValueType dstType, Operand ImmOd, ImmLeaf imm_type> &...

...FilterDAGBasicBlockName.empty() && + MatchFilterBB = (FilterDAGBasicBlockName.empty() || FilterDAGBasicBlockName == FuncInfo->MBB->getBasicBlock()->getName().str()); #endif — Mehdi > On Aug 1, 2015, at 11:07 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Simply replacing the && with || did not fix the issue. This issue still exists after making those changes. There is maybe some other code that needs to be changed also? > > Thanks. > > On Mon, Jul 27, 2015 at 12:45 PM, Ryan Taylor <ryta120...

I've tried all the types (both for result and Intrinsic ID), can't seem to find what cast is causing the issue here. On Fri, Jun 24, 2016 at 11:47 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > That's what I thought but I got the same error with: > > DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, > DAG.getTargetConstant(Intrinsic::my_intrinsic, DL, MVT::i16), LHS); > > Thanks. > > What should this call look like? > > > On Fri,...

...Base sub class of GPR to the MOV instruction, so it can't constrain it to Base and hence has to add the COPY. Now I just need to find out why it is ignoring the TableGen defined GPRBase for the MOV MI in favor of it's sub class GPR. Thanks. On Mon, Aug 24, 2015 at 8:34 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Quentin, > > It looks like firstCommonClass is returning a nullptr, which is odd > since the MOV should be using GPRBase (GPR and Base) and the NewVReg class > is Base. Maybe the ISel has decided to select the sub class GPR from > GPRBase and hence GP...

---------- Forwarded message ---------- From: Ryan Taylor <ryta1203 at gmail.com> Date: Thu, Dec 8, 2011 at 11:13 AM Subject: Re: [LLVMdev] GetElementPtr To: Reid Kleckner <reid.kleckner at gmail.com> There is no support for gep, it's my understanding that it's target-independent, so there's no reason to put the lowering in the target lowerin...

...ong? > > > >     Cheers, > >     Nicolai > > > > > > > > > >      > > >      > Thanks. > >      > > >      > On Mon, Aug 20, 2018 at 12:56 PM Ryan Taylor > <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com> > >     <mailto:ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> > >      > <mailto:ryta1203 at gmail.com <mailto:ryta1203 at gmail.com> > <mailto:ryta1203 at gmail.com <mailto:ryta1203...

It looks like this problem only exists on nested loops, ideas? On Thu, Jan 12, 2012 at 11:44 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Is it not a good idea to try and extract loops that have multiple exits? > > > On Thu, Jan 12, 2012 at 10:44 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > >> I am trying to use ExtractLoop() but I am getting segFaults: >> >> 0 op...

...owered into IR assuming an x86 architecture. The real problem is that I don't want the x86 code generation, I still want to deal in LLVM IR just with the GEP lowered, and it lowered for the x86 architecture is fine. Is there any way to do this? On Thu, Dec 8, 2011 at 11:39 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Or is it in the docs such that when you use the word "independent", you > really mean "independent of a particular target" and not actually "target > independent"? > > > On Thu, Dec 8, 2011 at 11:18 AM, Ryan Taylor <ryta1...

...is correct. > > Where does this code come from, and why do you think contracting to fma > is wrong? > > Cheers, > Nicolai > > > > > > > > Thanks. > > > > On Mon, Aug 20, 2018 at 12:56 PM Ryan Taylor <ryta1203 at gmail.com > <mailto:ryta1203 at gmail.com> > > <mailto:ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>>> wrote: > > > >     I'm curious why the condition to fuse is this: > > > >     // Floating-point mul...