search for: ryanrbaird

I forgot to mention, the generated file that has the tab is VPOGenAsmWriter.inc. On Sat, Sep 8, 2012 at 2:43 PM, ryan baird <ryanrbaird at gmail.com> wrote: > I'm building a target for the intermediate language of another compiler. > The other intermediate language is close to an assembly language (RTL, 1 > operation per line), so I based my target off of the Mips target. However, > the intermediate language i&...

I'm building a target for the intermediate language of another compiler. The other intermediate language is close to an assembly language (RTL, 1 operation per line), so I based my target off of the Mips target. However, the intermediate language i'm targetting does not support tabs before the instructions. I've looked through the files and found that the tab comes from the

...llvmdev-bounces at cs.uiuc.edu] On Behalf Of ryan baird Sent: Saturday, September 08, 2012 1:45 PM To: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] LLC always has a tab? I forgot to mention, the generated file that has the tab is VPOGenAsmWriter.inc. On Sat, Sep 8, 2012 at 2:43 PM, ryan baird <ryanrbaird at gmail.com<mailto:ryanrbaird at gmail.com>> wrote: I'm building a target for the intermediate language of another compiler. The other intermediate language is close to an assembly language (RTL, 1 operation per line), so I based my target off of the Mips target. However, the interm...

I am compiling the following code for the MIPS architecture: unsigned char trunc(float f) { return (unsigned char) f; } and it produces the following assembly (directives removed for convenience: trunc: trunc.w.s $f0, $f12 mfc1 $2, $f0 jr $ra nop However, this does not seem to produce the correct output for negative numbers. When I run the following code, I get

...gt; function that returns an unsigned char would ever return a 32 bit -1, > because that value does not fit the functions return type. > > > On Mon, Aug 6, 2012 at 2:03 PM, Eli Friedman <eli.friedman at gmail.com>wrote: > >> On Mon, Aug 6, 2012 at 12:43 PM, ryan baird <ryanrbaird at gmail.com> wrote: >> > I am compiling the following code for the MIPS architecture: >> > >> > unsigned char trunc(float f) { >> > return (unsigned char) f; >> > } >> > >> > and it produces the following assembly (directive...

I'm working on building a target for llvm that's the intermediate language of another compiler, so that the other compiler can benifit from llvm's optimization passes. I essentially made a copy of the mips backend, and then started changing the output to match the intermediate language of the compiler. Most of the output can be overriden, but I haven't figured out how to change

2012/9/9 ryan baird <ryanrbaird at gmail.com>: > I'm working on building a target for llvm that's the intermediate language > of another compiler, so that the other compiler can benifit from llvm's > optimization passes. > > I essentially made a copy of the mips backend, and then started changing the...

I just accidently sent a partially complete email, so this contains the rest (sorry!) I'm working on translating llvm's optimized intermediate code to another compiler's intermediate code, and I'm working on the PHI instruction. Here's an example phi instruction to help explain what I'm trying to do: %inc25 = phi i32 [ 1, %entry ], [ %inc, %for.body ] What I would want to

Ryan, I don't think I fully understand the problem you described, but please see the comments below. Hope this helps you solve the problem. On Sat, Oct 6, 2012 at 3:18 PM, ryan baird <ryanrbaird at gmail.com> wrote: > I'm working on a target based on the MIPS target, and when I copy f64 > values into 32 bit registers for calling functions, I need the operation to > work on a of 32 bit registers (because the language I'm translating to > isn't actually mips). I&...

Is there a pass I can use after reg2mem to get rid of occurances like this?: store i32 %cond, i32* %cond.reg2mem %cond.reload = load i32* %cond.reg2mem store i32 %cond.reload, i32* %cond4.reg2mem Essentially, in this case, reg2mem creates an extra memory space to store and load a value from just here, and never uses the value again; since this isn't efficient code, I'm wondering if

On Jan 23, 2013, at 3:45 PM, ryan baird <ryanrbaird at gmail.com> wrote: > I was reading about the order of optimizations in the code generation stage here: http://llvm.org/docs/CodeGenerator.html#the-high-level-design-of-the-code-generator > > This is the part that's interesting to me: > > 3. SSA-based Machine Code Optimiza...

I'm working on a target based on the MIPS target, and when I copy f64 values into 32 bit registers for calling functions, I need the operation to work on a of 32 bit registers (because the language I'm translating to isn't actually mips). I've been looking at how to do this, but I haven't been able to figure it out. Since the Mips target code is still really close to mine,

I was reading about the order of optimizations in the code generation stage here: http://llvm.org/docs/CodeGenerator.html#the-high-level-design-of-the-code-generator This is the part that's interesting to me: 3. SSA-based Machine Code Optimizations<http://llvm.org/docs/CodeGenerator.html#ssa-based-machine-code-optimizations>— This optional stage consists of a series of machine-code

I'm working on translating llvm's optimized intermediate code to another compiler's intermediate code, and I'm working on the PHI instruction. Here's an example phi instruction to help explain what I'm trying to do: %inc25 = phi i32 [ 1, %entry ], [ %inc, %for.body ] What I would want to do here is allocate some memory memory (i'm trying to use %phi1 = alloca i32,

Esentially, I'm working on a translator someone started building for llvm2.9 that translates an optimized .lln file to another intermediate language, and I'm porting it to 3.1. There is a new intrinsic that pops up in our test cases' lln files that never used to, llvm.lifetime.start. I looked up the description: "The 'llvm.lifetime.start' intrinsic specifies the start of

I'm translating llvm's intermediate representation, after optimization, to the intermediate representation of another optimizer. One of the problems I've run into is that llvm sometimes (although rarely) produces strangely sized integers after an opt pass with -O3 (in this example, 832 bits). I need to use 8, 16, or 32 bit integers for the other intermediate language. In short,

Is there a fast way to generate MIPS assembly from llc without using a specific instruction like sqrt.d (I want it to use the software call to Math.sqrt instead)?

Given an instruction and the basic block that it's in, is there an easy way to tell if the operands are ever referenced after the instruction? For example, if i have ... %mul = mul nsw i32 %a, %val %add = add nsw i32 %b, %val ... And I'm iterating through this basic block, can I tell when I get to the multiply instruction that another instruction is going to be using %val? Since I'm

Here's an example piece of code to show you what I'm trying to do (on llvm 3.1): class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, InstrItinClass itin, RegisterClass RC, bit isComm = 0>: FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), !strconcat("+$rd=$rs ",!strconcat(instr_asm, " $rt")),

I'm working on a target for the intermediate language of another compiler (so it can benifit from LLVM's optimization stages). I'm working on LLVM 3.1 for now. I started the translater as a copy of the MIPS target so that I can just modify it to produce the correct output. I basically want to replace all of the local variables and incoming parameters with values that look like this: