Displaying 5 results from an estimated 5 matches for "rwpi".
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rmpi
2015 Dec 04
3
[RFC][ARM] Add support for embedded position-independent code (ROPI/RWPI)
...ave a downstream patch (attached) which implements some new
addressing modes that enable position-independent code for small embedded
systems. Is this something that would be accepted upstream? I think the ARM
backend changes are fairly uncontroversial, but the clang changes introduce
a
lot of ROPI/RWPI specific changes in otherwise target-independent code. If
the
clang changes are not acceptable, it is still possible to use just the ARM
backend changes (with a smaller clang patch for command-line options only),
as
the C code which needs special lowering is rare, easy to work around and
easy
for a...
2015 Nov 25
2
ARM Static Base Register
Hi all,
I'm trying to see if I can use a global static base register instead of
PC-relative addressing. I see that I can easily reserve R9 in the ARM
Subtarget, but this doesn't let me use it. I found a TODO in
ARMAsmPrinter.cpp that refers to this:
// TODO: We currently only support either reserving the register, or
treating
// it as another callee-saved register, but not as SB or a
2020 Mar 23
2
RISC-V LLVM sync-up call 19 Mar 2020
...mes that the distance between the GP and the global data area, GOT and local scope variables is defined at link time.
__
Evandro Menezes ◊ SiFive ◊ Austin, TX
> On Mar 23, 2020, at 6:20, Sam Elliott <selliott at lowrisc.org> wrote:
>
> Eli,
>
> Yep, we’re looking at a ROPI/RWPI model for RISC-V and it is shaking out to be fairly similar to this model (though we’ve only been looking at it for 32-bit RISC-V).
>
> I suppose how I’m thinking about the difference between a ROPI/RWPI model and this compact model is in the former, you cannot know until load-time what the...
2020 Mar 20
2
RISC-V LLVM sync-up call 19 Mar 2020
Oh, I wasn’t really thinking about devices without an MMU where the addresses are physically separated. Makes sense.
This reminds me of rwpi on ARM; it has a sort of similar scheme of referring to data indirectly through a pointer, but it also changes the ABI to keep the pointer in a reserved register.
-Eli
From: Evandro Menezes <evandro.menezes at sifive.com>
Sent: Friday, March 20, 2020 12:28 PM
To: Eli Friedman <efriedma a...
2020 Mar 20
2
RISC-V LLVM sync-up call 19 Mar 2020
If I’m following correctly, there are two size-limited areas. One area, limited to 2GB, is the “text” area. This contains all the code. Then there’s a “global” area, limited to 4GB, which is pointed to by the global pointer. This contains the GOT, plus a flexible area that the object file can stick small bits of data into. And then outside of both of those, additional data is unlimited.
It