search for: rwlocks

...t; Nick > > Nicholas Piggin (6): > powerpc/powernv: must include hvcall.h to get PAPR defines > powerpc/pseries: move some PAPR paravirt functions to their own file > powerpc: move spinlock implementation to simple_spinlock > powerpc/64s: implement queued spinlocks and rwlocks > powerpc/pseries: implement paravirt qspinlocks for SPLPAR > powerpc/qspinlock: optimised atomic_try_cmpxchg_lock that adds the > lock hint > > arch/powerpc/Kconfig | 13 + > arch/powerpc/include/asm/Kbuild | 2 + > arch...

Hi, I think I found a bug in the rw_enter() implementation (emulation?) in libzpool, file /usr/src/lib/libzpool/common/kernel.c: void rw_enter(krwlock_t *rwlp, krw_t rw) { ASSERT(!RW_LOCK_HELD(rwlp)); ASSERT(rwlp->rw_owner != (void *)-1UL); ASSERT(rwlp->rw_owner != curthread); if (rw == RW_READER) (void) rw_rdlock(&rwlp->rw_lock); else (void)

...ot needed on FreeBSD, Darwin, OpenBSD, or Solaris, and probably not needed anywhere else (it doesn't seem to be documented in glibc, but there's always a chance that they followed the spec). Unless someone can nominate a platform that doesn't follow the spec and does default to shared rwlocks, I'd suggest removing all of the code related to attr in that function and just passing NULL as the attribute parameter in all cases. I'm happy to make this change if no one objects. David On 14 Feb 2010, at 14:09, Vincent Richomme wrote: > On Sun, 14 Feb 2010 14:26:38 +0100, Vincent...

...on FreeBSD, Darwin, OpenBSD, or Solaris, and probably not needed anywhere else (it doesn't seem to be documented in glibc, but there's always a chance that they followed the spec). > > Unless someone can nominate a platform that doesn't follow the spec and does default to shared rwlocks, I'd suggest removing all of the code related to attr in that function and just passing NULL as the attribute parameter in all cases. > > I'm happy to make this change if no one objects. > > David > > On 14 Feb 2010, at 14:09, Vincent Richomme wrote: > >> On S...

Excerpts from Will Deacon's message of July 2, 2020 6:02 pm: > On Thu, Jul 02, 2020 at 05:48:36PM +1000, Nicholas Piggin wrote: >> diff --git a/arch/powerpc/include/asm/qspinlock.h b/arch/powerpc/include/asm/qspinlock.h >> new file mode 100644 >> index 000000000000..f84da77b6bb7 >> --- /dev/null >> +++ b/arch/powerpc/include/asm/qspinlock.h >> @@ -0,0

Excerpts from Will Deacon's message of July 2, 2020 8:35 pm: > On Thu, Jul 02, 2020 at 08:25:43PM +1000, Nicholas Piggin wrote: >> Excerpts from Will Deacon's message of July 2, 2020 6:02 pm: >> > On Thu, Jul 02, 2020 at 05:48:36PM +1000, Nicholas Piggin wrote: >> >> diff --git a/arch/powerpc/include/asm/qspinlock.h b/arch/powerpc/include/asm/qspinlock.h

On 7/7/20 1:57 AM, Nicholas Piggin wrote: > Yes, powerpc could certainly get more performance out of the slow > paths, and then there are a few parameters to tune. > > We don't have a good alternate patching for function calls yet, but > that would be something to do for native vs pv. > > And then there seem to be one or two tunable parameters we could > experiment

On Tue, Jul 07, 2020 at 11:33:45PM -0400, Waiman Long wrote: > From 5d7941a498935fb225b2c7a3108cbf590114c3db Mon Sep 17 00:00:00 2001 > From: Waiman Long <longman at redhat.com> > Date: Tue, 7 Jul 2020 22:29:16 -0400 > Subject: [PATCH 2/9] locking/pvqspinlock: Introduce > CONFIG_PARAVIRT_QSPINLOCKS_LITE > > Add a new PARAVIRT_QSPINLOCKS_LITE config option that allows

On Tue, Jul 07, 2020 at 03:57:06PM +1000, Nicholas Piggin wrote: > Yes, powerpc could certainly get more performance out of the slow > paths, and then there are a few parameters to tune. Can you clarify? The slow path is already in use on ARM64 which is weak, so I doubt there's superfluous serialization present. And Will spend a fair amount of time on making that thing guarantee forward

On Wed, Jul 08, 2020 at 07:54:34PM -0400, Waiman Long wrote: > On 7/8/20 4:41 AM, Peter Zijlstra wrote: > > On Tue, Jul 07, 2020 at 03:57:06PM +1000, Nicholas Piggin wrote: > > > Yes, powerpc could certainly get more performance out of the slow > > > paths, and then there are a few parameters to tune. > > Can you clarify? The slow path is already in use on ARM64

On 7/23/20 9:30 AM, Nicholas Piggin wrote: >> I would prefer to extract out the pending bit handling code out into a >> separate helper function which can be overridden by the arch code >> instead of breaking the slowpath into 2 pieces. > You mean have the arch provide a queued_spin_lock_slowpath_pending > function that the slow path calls? > > I would actually prefer

On Thu, Jul 02, 2020 at 05:48:36PM +1000, Nicholas Piggin wrote: > diff --git a/arch/powerpc/include/asm/qspinlock.h b/arch/powerpc/include/asm/qspinlock.h > new file mode 100644 > index 000000000000..f84da77b6bb7 > --- /dev/null > +++ b/arch/powerpc/include/asm/qspinlock.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _ASM_POWERPC_QSPINLOCK_H >

On Thu, Jul 02, 2020 at 05:48:36PM +1000, Nicholas Piggin wrote: > diff --git a/arch/powerpc/include/asm/qspinlock.h b/arch/powerpc/include/asm/qspinlock.h > new file mode 100644 > index 000000000000..f84da77b6bb7 > --- /dev/null > +++ b/arch/powerpc/include/asm/qspinlock.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _ASM_POWERPC_QSPINLOCK_H >

...his system is running Debian unstable and has the following auto* > > versions: > > I'm currently in the process of changing the setup for using rwlock_t, > not all systems have them (they are a later posix spec) and are only > used by one module (avl). > Err.. what? The rwlocks are absolutely _critical_ for icecast (though probably not for ices/libshout). You cannot remove them or make them optional. Mike <p>--- >8 ---- List archives: http://www.xiph.org/archives/ icecast project homepage: http://www.icecast.org/ To unsubscribe from this list, send a message t...

On 7/21/20 7:08 AM, Nicholas Piggin wrote: > diff --git a/arch/powerpc/include/asm/qspinlock.h b/arch/powerpc/include/asm/qspinlock.h > index b752d34517b3..26d8766a1106 100644 > --- a/arch/powerpc/include/asm/qspinlock.h > +++ b/arch/powerpc/include/asm/qspinlock.h > @@ -31,16 +31,57 @@ static inline void queued_spin_unlock(struct qspinlock *lock) > > #else > extern

Nicholas Piggin <npiggin at gmail.com> writes: > These have shown significantly improved performance and fairness when > spinlock contention is moderate to high on very large systems. > > [ Numbers hopefully forthcoming after more testing, but initial > results look good ] Would be good to have something here, even if it's preliminary. > Thanks to the fast path,

On 7/8/20 1:10 AM, Nicholas Piggin wrote: > Excerpts from Waiman Long's message of July 8, 2020 1:33 pm: >> On 7/7/20 1:57 AM, Nicholas Piggin wrote: >>> Yes, powerpc could certainly get more performance out of the slow >>> paths, and then there are a few parameters to tune. >>> >>> We don't have a good alternate patching for function calls yet,

...; Nicholas Piggin (6): >> powerpc/powernv: must include hvcall.h to get PAPR defines >> powerpc/pseries: move some PAPR paravirt functions to their own file >> powerpc: move spinlock implementation to simple_spinlock >> powerpc/64s: implement queued spinlocks and rwlocks >> powerpc/pseries: implement paravirt qspinlocks for SPLPAR >> powerpc/qspinlock: optimised atomic_try_cmpxchg_lock that adds the >> lock hint >> >> arch/powerpc/Kconfig | 13 + >> arch/powerpc/include/asm/Kbuild...

...; Nicholas Piggin (6): >> powerpc/powernv: must include hvcall.h to get PAPR defines >> powerpc/pseries: move some PAPR paravirt functions to their own file >> powerpc: move spinlock implementation to simple_spinlock >> powerpc/64s: implement queued spinlocks and rwlocks >> powerpc/pseries: implement paravirt qspinlocks for SPLPAR >> powerpc/qspinlock: optimised atomic_try_cmpxchg_lock that adds the >> lock hint >> >> arch/powerpc/Kconfig | 13 + >> arch/powerpc/include/asm/Kbuild...

.../powerpc/Kconfig b/arch/powerpc/Kconfig index 9fa23eb320ff..b17575109876 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -145,6 +145,8 @@ config PPC select ARCH_SUPPORTS_ATOMIC_RMW select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_CMPXCHG_LOCKREF if PPC64 + select ARCH_USE_QUEUED_RWLOCKS if PPC_QUEUED_SPINLOCKS + select ARCH_USE_QUEUED_SPINLOCKS if PPC_QUEUED_SPINLOCKS select ARCH_WANT_IPC_PARSE_VERSION select ARCH_WEAK_RELEASE_ACQUIRE select BINFMT_ELF @@ -490,6 +492,17 @@ config HOTPLUG_CPU Say N if you are unsure. +config PPC_QUEUED_SPINLOCKS + bool "Queued s...