search for: rvloc

...owered in certain order, that is dangerous. It's probably better to check whether the last call is a tail call on the fly as you are processing the return node. 8. - - SDOperand Chain = Op.getOperand(0); - SDOperand Flag; - - // Copy the result values into the output registers. - if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() || - RVLocs[0].getLocReg() != X86::ST0) { - for (unsigned i = 0; i != RVLocs.size(); ++i) { - CCValAssign &VA = RVLocs[i]; - assert(VA.isRegLoc() && "Can only return in registers!"); - Chain = DAG.getCopyToReg(Chain,...

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

...s. 3. XXXISelLowering::LowerReturn() should add return value registers to the RET_FLAG node instead of calling MRI.addLiveOut(): --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1590,14 +1590,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, RVLocs, *DAG.getContext()); CCInfo.AnalyzeReturn(Outs, RetCC_X86); - // Add the regs to the liveout set for the function. - MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); - for (unsigned i = 0; i != RVLocs.size(); ++i) - if (RVLocs[i].isRegLoc() && !MRI.isLiveOut...

...s probably better to check > whether the last call is a tail call on the fly as you are processing > the return node. Will do so. > 8. > - > - SDOperand Chain = Op.getOperand(0); > - SDOperand Flag; > - > - // Copy the result values into the output registers. > - if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() || > - RVLocs[0].getLocReg() != X86::ST0) { > - for (unsigned i = 0; i != RVLocs.size(); ++i) { > - CCValAssign &VA = RVLocs[i]; > - assert(VA.isRegLoc() && "Can only return in registers!"); > - Chain...