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rv32imc
2020 Sep 29
2
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
...upport for the RISC-V V extension is now
developed upstream. I assume that this means that the features are now
available from LLVM master.
However, when I pull the current master and build it and try to compile
the sample code with llc (specifying the target with
--mtriple=riscv32-unkown-none-rv32imv ), I get following error:
error: ../llvm-project/build/bin/llc: test.ll:4:18: error: use of
undefined value '@llvm.riscv.vsetvl'
It seems that the V extension is available, since `llc -march=riscv32
-mattr=help` lists it:
Available features for this target:
...
experimental-v ...
2020 Oct 29
0
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
...for the RISC-V V extension is now developed upstream. I assume that this means that the features are now available from LLVM master.
>
> However, when I pull the current master and build it and try to compile the sample code with llc (specifying the target with --mtriple=riscv32-unkown-none-rv32imv ), I get following error:
>
> error: ../llvm-project/build/bin/llc: test.ll:4:18: error: use of undefined value '@llvm.riscv.vsetvl'
>
> It seems that the V extension is available, since `llc -march=riscv32 -mattr=help` lists it:
>
> Available features for this target:...