search for: rv32i

...nt status * A full, regularly rebased patchset can be found here <https://github.com/lowRISC/riscv-llvm>. * 16 of these patches have been put up for review so far. 7 have been committed, and 8 are awaiting review. * The vast majority of the GCC torture suite compiles and runs at O0, targeting RV32I. 1315 out of 1352 compile and run (32 compile-time failures, 5 run-time failures). * I intend to keep <http://www.lowrisc.org/llvm/status> updated with status, test results etc. ## Next steps and getting involved The plan has always been to work from the MC-layer upwards towards reliable RV3...

...t subscribed to this mailing list. I am trying to test riscv llvm tools in QEMU using llvm testsuite. As a trial i am trying only the Single Source C Regression folder. The steps that i took are : ]$ cmake -DCMAKE_C_COMPILER=/opt/riscv-tools/bin/clang -DCMAKE_C_FLAGS="--target=riscv32 -march=rv32i -mabi=ilp32" -DCMAKE_CXX_COMPILER=/opt/riscv-tools/bin/clang -DCMAKE_CXX_FLAGS="--target=riscv32 -march=rv32i -mabi=ilp32" -DCMAKE_EXE_LINKER_FLAGS="-lm" -DTEST_SUITE_RUN_UNDER=/opt/qemu/bin/qemu-riscv32 -DTEST_SUITE_COLLECT_STATS=OFF -DTEST_SUITE_USER_MODE_EMULATION=ON -DT...

...and 64-bit variants and also supports a compressed variant, allowing 16-bit instructions to be freely intermingled with the standard 32-bit representations. The standard is structured to allow implementers to choose appropriate subsets to support, for instance a micro-controller might support 'RV32I' (32-bit RISC-V with the integer instructions) and an application core running Linux might implement RV64IMAFD (commonly shortened to RV64G: 64-bit with integer instructions, the multiply extension, atomics, and single and double precision floating point). A generous portion of the opcode space...

...rce, a github clone from today: clang version 11.0.0 (https://github.com/llvm/llvm-project.git 91aa67bf290bc7f877b1b90128284863bc31aa43) I compiled a small program: #include <stdint.h> int main() { uint8_t a = 2; uint8_t b = 5; uint8_t c = a * b; } $ clang -c -target riscv32 -march=rv32imc -g main.c Works fine. The dumped assembly seems to not know about the multiply instruction - is that expected? See offset 1e in the listing below. Happily, the opcode value does appear to match the MUL instruction. $ llvm-objdump -S main.o main.o: file format ELF32-riscv Disassembly of secti...

...ad/draft-20180612-548fd40/riscv-spec.pdf>, which incorporates work from the Memory Consistency Model Task Group to define the memory model. RISC-V implements a weak memory model. For those not familiar, RISC-V is a modular ISA, with standard extensions indicated by single letters. Baseline 'RV32I' or 'RV64I' instruction sets don't support atomic operations beyond fences. However the RV32A and RV64A instruction set extensions introduce AMOs (Atomic Memory Operations) and LR/SC (load-linked/store-conditional on other architectures). 32-bit atomic operations are supported nativ...

....org/rL313362). * GetElementPtr merging is now undone around indirect branches in some cases. This is another optimisation benchmarked using the Python interpreter loop, this time offering a 5% performance improvement. [r312930](http://reviews.llvm.org/rL312930). * MC-layer support for all RISC-V RV32I instruction has been committed, as well as disassembly support. [r313485](http://reviews.llvm.org/rL313485), [r313486](http://reviews.llvm.org/rL313486). * The llvm-dwarfdump command line parameter naming has been updated, as [discussed](http://lists.llvm.org/pipermail/llvm-dev/2017-September/1173...

...;, the RISC-V backend has i64 as the only legal integer type for the RV64 target. Thanks to variable-sized register class support, this means there is no need for duplication of either patterns or instruction definitions for RV32 and RV64. It's worth noting that RV64I is a different base ISA to RV32I. Rather than adding 64-bit operations, it re-defines the operations as 64-bit and introduces a small number of 'W' suffixed instructions such as ADDW, SLLW etc to operate on 32-bit values. There are some challenges though. Consider the variable-length shifts introduced in RV64I. SLLW, SRLW...