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...roup to define the memory model. RISC-V implements a weak memory model. For those not familiar, RISC-V is a modular ISA, with standard extensions indicated by single letters. Baseline 'RV32I' or 'RV64I' instruction sets don't support atomic operations beyond fences. However the RV32A and RV64A instruction set extensions introduce AMOs (Atomic Memory Operations) and LR/SC (load-linked/store-conditional on other architectures). 32-bit atomic operations are supported natively on RV32, and both 32 and 64-bit atomic operations support natively on RV64. AMOs such as 'amoadd.w...