Displaying 19 results from an estimated 19 matches for "rt_control".
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rtc_control
2014 May 26
2
Implement buffer_clear for nvc0
Hi, please review the following patch!
Thanks,
Tobias Klausmann
2015 Jan 02
2
[PATCH] nv50: enable texture compression
...;
}
+ BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
+ PUSH_DATA(push, dev->drm_version >= 0x01000101);
+
+ BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
+ for (i = 0; i < 8; ++i)
+ PUSH_DATA(push, dev->drm_version >= 0x01000101);
+
BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
PUSH_DATA (push, 1);
@@ -871,7 +878,7 @@ nv50_screen_create(struct nouveau_device *dev)
if (!nv50_blitter_create(screen))
goto fail;
- nv50_screen_init_hwctx(screen);
+ nv50_screen_init_hwctx(dev, screen);
nouveau_fence_new(&screen->base, &screen->ba...
2014 Jun 14
0
[PATCH 2/3] nvc0: mark scissor in nvc0_clear_{}
...ce.c
@@ -298,6 +298,7 @@ nvc0_clear_render_target(struct pipe_context *pipe,
BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
PUSH_DATA (push, ( width << 16) | dstx);
PUSH_DATA (push, (height << 16) | dsty);
+ nvc0->scissors_dirty |= 1;
BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
PUSH_DATA (push, 1);
@@ -447,6 +448,7 @@ nvc0_clear_buffer(struct pipe_context *pipe,
BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
PUSH_DATA (push, width << 16);
PUSH_DATA (push, height << 16);
+ nvc0->scissors_dirty |= 1;
IMMED_NVC0(push, NVC0_3D...
2014 May 26
0
[PATCH] nvc0: Implement buffer_clear for this type of hardware
...f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
+ PUSH_DATA (push, 1);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
+ PUSH_DATAh(push, buf->address + offset);
+ PUSH_DATA (push, buf->address + offset);
+
+ PUSH_DATA (push, width * data_size);
+ PUSH_DATA (push, height);
+
+ PUSH_DATA (push,...
2014 May 21
2
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...lt; 16) | dstx);
> + PUSH_DATA (push, (height << 16) | dsty);
> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
> + PUSH_DATA (push, 8192 << 16);
> + PUSH_DATA (push, 8192 << 16);
> + nv50->scissors_dirty |= 1;
> +
> BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
> PUSH_DATA (push, 1);
> BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
> @@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe,
> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
> }
>
> - nv50->dirty |= NV50_NEW_...
2014 May 27
1
[PATCH V3] nvc0: implement clear_buffer
...SH_DATAf(push, color.f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
+ PUSH_DATAh(push, buf->address + offset);
+ PUSH_DATA (push, buf->address + offset);
+
+ PUSH_DATA (push, width * data_size);
+ PUSH_DATA (push, height);
+
+ PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
+ PUSH_DATA...
2014 Jun 14
7
[PATCH 0/3] ARB_viewport_array for nvc0
This patch-series implements the ARB_viewport_array for nvc0 and does
a little house-cleanig afterwords.
Tobias Klausmann (3):
nvc0: implement multiple viewports/scissors, enable ARB_viewport_array
nvc0: mark scissor in nvc0_clear_{}
nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer
.../drivers/nouveau/codegen/nv50_ir_driver.h | 1 -
2014 May 26
1
[PATCH V2] nvc0: implement clear_buffer
...f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
+ PUSH_DATAh(push, buf->address + offset);
+ PUSH_DATA (push, buf->address + offset);
+
+ PUSH_DATA (push, width * data_size);
+ PUSH_DATA (push, height);
+
+ PUSH_DATA (push, nvc0_format_table[dst_fmt]....
2014 May 20
0
[PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...+ PUSH_DATA (push, ( width << 16) | dstx);
+ PUSH_DATA (push, (height << 16) | dsty);
+ BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
+ PUSH_DATA (push, 8192 << 16);
+ PUSH_DATA (push, 8192 << 16);
+ nv50->scissors_dirty |= 1;
+
BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
@@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe,
(z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
}
- nv50->dirty |= NV50_NEW_FRAMEBUFFER;
+ nv50->dirty |=...
2014 May 21
0
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...PUSH_DATA (push, (height << 16) | dsty);
>> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
>> + PUSH_DATA (push, 8192 << 16);
>> + PUSH_DATA (push, 8192 << 16);
>> + nv50->scissors_dirty |= 1;
>> +
>> BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
>> PUSH_DATA (push, 1);
>> BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
>> @@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe,
>> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
>> }
>>
>> - n...
2015 Jan 02
0
[PATCH] nv50: enable texture compression
...ion >= 0x01000101);
screen->base.device
And then no need to pass dev in, I think.
> +
> + BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
> + for (i = 0; i < 8; ++i)
> + PUSH_DATA(push, dev->drm_version >= 0x01000101);
> +
> BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
> PUSH_DATA (push, 1);
>
> @@ -871,7 +878,7 @@ nv50_screen_create(struct nouveau_device *dev)
> if (!nv50_blitter_create(screen))
> goto fail;
>
> - nv50_screen_init_hwctx(screen);
> + nv50_screen_init_hwctx(dev, screen);
>
> nouveau_fence_...
2015 Jan 02
1
[PATCH v2] nv50: enable texture compression
On 03.01.2015 00:20, Ilia Mirkin wrote:
> On Fri, Jan 2, 2015 at 6:09 PM, Tobias Klausmann
> <tobias.johannes.klausmann at mni.thm.de> wrote:
>> We enable compression only for some supported formats
>>
>> Suggested-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
>> ---
2015 Jan 02
2
[PATCH v2] nv50: enable texture compression
...(ZETA_COMP_ENABLE), 1);
+ PUSH_DATA(push, screen->base.device->drm_version >= 0x01000101);
+
+ BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
+ for (i = 0; i < 8; ++i)
+ PUSH_DATA(push, screen->base.device->drm_version >= 0x01000101);
+
BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
PUSH_DATA (push, 1);
--
2.2.1
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
I went through the gallium-nine tree and picked out nouveau patches that are
general bug-fixes. The first bunch I'd like to also get into 10.2. I've
reviewed all of them and they make sense to me, but sending them out for
public review as well in case there are any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull
2014 Sep 01
2
[PATCH 1/3] nv50: set the miptree address when clearing bo's in vp2 init
The mt address is about to be used more, make sure it's set
appropriately.
Reported-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable at lists.freedesktop.org>
---
src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 ++
1 file
2015 Nov 26
9
[mesa 1/9] nouveau: bump required libdrm version to 2.4.66
From: Ben Skeggs <bskeggs at redhat.com>
Signed-off-by: Ben Skeggs <bskeggs at redhat.com>
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 4016871..c02ee61 100644
--- a/configure.ac
+++ b/configure.ac
@@ -73,7 +73,7 @@ LIBDRM_RADEON_REQUIRED=2.4.56
LIBDRM_AMDGPU_REQUIRED=2.4.63
LIBDRM_INTEL_REQUIRED=2.4.61
2015 Dec 16
11
[mesa v3 1/9] nouveau: bump required libdrm version to 2.4.66
From: Ben Skeggs <bskeggs at redhat.com>
v2. forgot bump for non-gallium driver
Signed-off-by: Ben Skeggs <bskeggs at redhat.com>
---
configure.ac | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/configure.ac b/configure.ac
index b6680d0..965c6f7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -72,8 +72,8 @@ LIBDRM_REQUIRED=2.4.60
2014 Jan 15
3
[PATCH] nv50, nvc0: don't crash on a null cbuf
...bind NULL colorbuffers
as specified by glDrawBuffers).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Not sure whether something needs to be done to clear out the old RT_* settings
for that index buffer, or if things are cleared out implicitly. Perhaps
instead of skipping indices, RT_CONTROL needs to be adjusted with the
appropriate indices?
src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 14 +++++++++++---
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c | 14 +++++++++++---
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv...
2015 Nov 27
13
[mesa v2 1/9] nouveau: bump required libdrm version to 2.4.66
From: Ben Skeggs <bskeggs at redhat.com>
Signed-off-by: Ben Skeggs <bskeggs at redhat.com>
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 4016871..c02ee61 100644
--- a/configure.ac
+++ b/configure.ac
@@ -73,7 +73,7 @@ LIBDRM_RADEON_REQUIRED=2.4.56
LIBDRM_AMDGPU_REQUIRED=2.4.63
LIBDRM_INTEL_REQUIRED=2.4.61