Displaying 20 results from an estimated 48 matches for "rt1".
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2010 Nov 11
2
[LLVMdev] defining types structurally equivalent to a recursive type
Hi all,
http://www.llvm.org/docs/ProgrammersManual.html#BuildRecType suggests
us to define recursive types via opaque and refine. Since LLVM has
structural types, %rt = type { %rt* } and %rt1 = type { %rt* } should
be same structurally. I tested the following code,
%rt = type { %rt* }
%rt1 = type { %rt* }
define i32 @main() nounwind {
entry:
%0 = alloca %rt ; <%rt*> [#uses=1]
%1 = alloca %rt ; <%rt*> [#use...
2010 Nov 11
0
[LLVMdev] defining types structurally equivalent to a recursive type
...Thu, Nov 11, 2010 at 8:28 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote:
> Hi all,
>
> http://www.llvm.org/docs/ProgrammersManual.html#BuildRecType suggests
> us to define recursive types via opaque and refine. Since LLVM has
> structural types, %rt = type { %rt* } and %rt1 = type { %rt* } should
> be same structurally. I tested the following code,
>
> %rt = type { %rt* }
> %rt1 = type { %rt* }
>
> define i32 @main() nounwind {
> entry:
> %0 = alloca %rt ; <%rt*> [#uses=1]
> %1 = alloca %rt ...
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...of the operation in this H/W platform:
ADD R3.ab, R1.abab, R2.bbaa
it means
Add 'abab' channel of R1 and 'bbaa' channel of R2, and put the
result into the 'ab' channel of R3.
It's complicate.
Imagine a non-existed temp register named 'Rt1', the content of its
'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
and imagine another non-existed temp register named 'Rt2', the content of
its 'a','b','c','d' channel...
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
....ab, R1.abab, R2.bbaa
>
> > it means
>
> > Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> > put the result into the 'ab' channel of R3.
>
> > It's complicate.
> > Imagine a non-existed temp register named 'Rt1', the content of its
> > 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> > and imagine another non-existed temp register named 'Rt2', the
> > content of its 'a','b'...
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...; ADD R3.ab, R1.abab, R2.bbaa
>
> it means
>
> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> put the result into the 'ab' channel of R3.
>
> It's complicate.
> Imagine a non-existed temp register named 'Rt1', the content of its
> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> and imagine another non-existed temp register named 'Rt2', the
> content of its 'a','b','c',&...
2010 Jul 24
1
Bridging Issues with Xen
...peth1
vif0.0
Tried To Install Guest Via Virt-Install
virt-install -p --location
"http://10.0.0.3/cblr/links/CentOS-5.2-xen-x86_64" -b xenbr1 -m
"03:ac:5a:00:02:29" --nographics --file /dev/xenvg/lv-rt1-d --ram 7500 -x
"ks=http://10.0.0.3/cblr/svc/op/ks/profile/CentOS-5.2-x86_64" --name="rt1"
--force
or Just By Booting A premade config file :
name = "rt1-d"
uuid = "2e656868-91d3-fa3e-300c-3a8a9909cf09"
kernel = "/etc/xen/vmlinuz"
ramdisk = "...
2017 Oct 11
1
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
...3_ede-asm_64.S b/arch/x86/crypto/des3_ede-asm_64.S
index 8e49ce117494..4bbd3ec78df5 100644
--- a/arch/x86/crypto/des3_ede-asm_64.S
+++ b/arch/x86/crypto/des3_ede-asm_64.S
@@ -138,21 +138,29 @@
movzbl RW0bl, RT2d; \
movzbl RW0bh, RT3d; \
shrq $16, RW0; \
- movq s8(, RT0, 8), RT0; \
- xorq s6(, RT1, 8), to; \
+ leaq s8(%rip), RW1; \
+ movq (RW1, RT0, 8), RT0; \
+ leaq s6(%rip), RW1; \
+ xorq (RW1, RT1, 8), to; \
movzbl RW0bl, RL1d; \
movzbl RW0bh, RT1d; \
shrl $16, RW0d; \
- xorq s4(, RT2, 8), RT0; \
- xorq s2(, RT3, 8), to; \
+ leaq s4(%rip), RW1; \
+ xorq (RW1, RT2, 8), RT0; \
+ leaq...
2008 Nov 21
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...;>
>>> it means
>>
>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>> put the result into the 'ab' channel of R3.
>>
>>> It's complicate.
>>> Imagine a non-existed temp register named 'Rt1', the content of its
>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
>>> and imagine another non-existed temp register named 'Rt2', the
>>> content of its 'a','...
2003 Dec 29
1
Agent setup
Dear Group,
I have been successful in setting up the Agents, queues and getting agents
to log in.
Is there a way that I could configure the system so that the agent is called
back. i.e. the agent logs into the system, a call is destined for them and
their phone rings.
If some one has this setup I would be very interested in hearing from them.
Warm Regards and Thanks
---------------
Shad
2005 Nov 25
7
tcpdump not working with imq0 devices
On my debian woody (kernel 2.4.31) the tcpdump
doesn''t work with imq0 devices. If I try to tcpdump
imq devices there is no packet seen:
[...]
rt1:~# tcpdump -n -i imq0
Warning: arptype 65535 not supported by libpcap - falling back to cooked socket
tcpdump: WARNING: imq0: no IPv4 address assigned
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on imq0, link-type LINUX_SLL (Linux cooked), capture size 6...
2008 Nov 20
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...;>
>>> it means
>>
>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>> put the result into the 'ab' channel of R3.
>>
>>> It's complicate.
>>> Imagine a non-existed temp register named 'Rt1', the content of its
>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
>>> and imagine another non-existed temp register named 'Rt2', the
>>> content of its 'a','...
2005 Jun 29
0
Upload shaper problem
Hello guys,
I am experiencing a strange behaviour with HTB. Here is my situation:
Test PC -------- internet ------------- ISP ----- fiber connection ---------
(eht2) RT1 (eth1) --------- wireless connection ------------ (eth4) RT2
(eth0) -------- users
RT1 - Slackware router
RT2 - Slackware router
Delay between Test PC and ISP is approx 450 ms.
I have the following shapers
RT1 ETH2 - dedicated bandwidth for Test PC 40kbps
RT2 ETH4 - dedicated band...
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...t;> it means
>
> >>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> >>> put the result into the 'ab' channel of R3.
>
> >>> It's complicate.
> >>> Imagine a non-existed temp register named 'Rt1', the content of its
> >>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> >>> and imagine another non-existed temp register named 'Rt2', the
> >>> content of its ...
2004 Jun 02
0
how to route based on link load?
...| rt 1 |--------| rt 2 |#####| subnet 2 |
+----------+ +------+ +------+ +----------+
\ /
\ +------+ /
\| rt 3 |/
+------+
the bandwidth of the links is as follows:
sn1 - rt1 100mbit
sn2 - rt2 100mbit
rt1 - rt2 - rt3 10mbit
now there are multiple flows from sn1 to sn2.
if the load on the prefered link (rt1-rt2) is 80% or more
i want to utilisize the rt1-rt3-rt2 route as well.
but only in this case - not normaly.
so i think ecmp with weig...
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...t;> it means
>
> >>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> >>> put the result into the 'ab' channel of R3.
>
> >>> It's complicate.
> >>> Imagine a non-existed temp register named 'Rt1', the content of its
> >>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> >>> and imagine another non-existed temp register named 'Rt2', the
> >>> content of its ...
2008 Nov 24
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...>
>>>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>>>> put the result into the 'ab' channel of R3.
>>
>>>>> It's complicate.
>>>>> Imagine a non-existed temp register named 'Rt1', the content of
>>>>> its
>>>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of
>>>>> R1,
>>>>> and imagine another non-existed temp register named ...
2008 Nov 22
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...>
>>>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
>>>>> put the result into the 'ab' channel of R3.
>>
>>>>> It's complicate.
>>>>> Imagine a non-existed temp register named 'Rt1', the content of
>>>>> its
>>>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of
>>>>> R1,
>>>>> and imagine another non-existed temp register named ...
2008 Nov 24
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...t;>>> Add 'abab' channel of R1 and 'bbaa' channel of R2, and
> >>>>> put the result into the 'ab' channel of R3.
>
> >>>>> It's complicate.
> >>>>> Imagine a non-existed temp register named 'Rt1', the content of
> >>>>> its
> >>>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of
> >>>>> R1,
> >>>>> and imagine another non-existed te...
2013 Feb 20
1
Access puppet hash name in templates
Hi,
I''ve defined a hash like so in my nodes.pp:
net::addr { "eth5":
rt => {
rt1 => {
address => ''192.168.10.0'',
netmask => ''255.255.255.0'',
gateway => ''192.5.28.19'',
src => ''192.5.28.21''...
2008 Nov 24
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...channel of R1 and 'bbaa' channel of R2,
>>>>>>> and
>>>>>>> put the result into the 'ab' channel of R3.
>>
>>>>>>> It's complicate.
>>>>>>> Imagine a non-existed temp register named 'Rt1', the content of
>>>>>>> its
>>>>>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of
>>>>>>> R1,
>>>>>>> and imagine another non-ex...