Displaying 8 results from an estimated 8 matches for "rsrc2".
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2007 Apr 23
4
[LLVMdev] Instruction pattern type inference problem
...why that's the case.
This isn't just the results of instructions, but also immediate
values as well. It seems to affect a smattering of node types. Any
insights?
For instance:
where GPRegs contains types [i32, f32]
def BEQ : IF8<Opc.BEQ,
(ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
"beq $Rsrc1, $Rsrc2, $SImm16",
[(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
$SImm16)], s_br>;
Tablegen reports:
BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2,
SETEQ:Other), (bb:Other):$SImm16)
as soon...
2007 Apr 23
0
[LLVMdev] Instruction pattern type inference problem
...9;t just the results of instructions, but also immediate
> values as well. It seems to affect a smattering of node types. Any
> insights?
>
> For instance:
>
> where GPRegs contains types [i32, f32]
>
> def BEQ : IF8<Opc.BEQ,
> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
> "beq $Rsrc1, $Rsrc2, $SImm16",
> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
> $SImm16)], s_br>;
>
> Tablegen reports:
> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2,
> SETEQ:Other),...
2007 Apr 23
1
[LLVMdev] Instruction pattern type inference problem
..., but also immediate
>> values as well. It seems to affect a smattering of node types. Any
>> insights?
>>
>> For instance:
>>
>> where GPRegs contains types [i32, f32]
>>
>> def BEQ : IF8<Opc.BEQ,
>> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
>> "beq $Rsrc1, $Rsrc2, $SImm16",
>> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
>> $SImm16)], s_br>;
>>
>> Tablegen reports:
>> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$R...
2007 Apr 23
0
[LLVMdev] Instruction pattern type inference problem
...just the results of instructions, but also immediate
> values as well. It seems to affect a smattering of node types. Any
> insights?
>
> For instance:
>
> where GPRegs contains types [i32, f32]
>
> def BEQ : IF8<Opc.BEQ,
> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
> "beq $Rsrc1, $Rsrc2, $SImm16",
> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
> $SImm16)], s_br>;
>
> Tablegen reports:
> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:
> $Rsrc2, SETEQ:Othe...
2017 Jun 05
2
Backend implementation for an architecture with only majority operation instruction
...at 8:22 PM, Sean Silva <chisophugis at gmail.com> wrote:
> I'm having a hard time grasping what this ISA actually looks like.
>
> When you say that it has a single instruction that is a majority function,
> I assume something like this:
>
> MAJ rDst <- rSrc0, rSrc1, rSrc2
> Semantics:
> for (int i = 0; i < REGISTER_WIDTH; i++) {
> rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]);
> }
> Where maj(a, b, c) = (a & b) | (a & c) | (b & c)
>
> But that doesn't make sense given your question.
>
> MAJ is a bitwise operation, so how...
2009 Apr 16
2
[LLVMdev] How do I model MUL with multiply-accumulate instruction?
...ly-and-accumulate. The result goes into a special register that
can destructively read at the end of a sequence of multiply-adds. The
following sequence is required to so a simple multiply:
acc r0 # clear accumulator, discarding its value (r0 reads as 0,
and sinks writes)
mac rSRC1, rSRC2 # multiply sources, store result in accumulator
acc rDEST # fetch accumulator value to rDEST
What's the best way to model simple MUL as this 3-insn sequence in the
LLVM backend?
Should the internal accumulation register be explicitly modeled as its
own register class with a pattern...
2017 Jun 02
5
Backend implementation for an architecture with only majority operation instruction
Hello everyone,
I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what
2009 Apr 17
0
[LLVMdev] How do I model MUL with multiply-accumulate instruction?
...result goes into a special register that
> can destructively read at the end of a sequence of multiply-adds. The
> following sequence is required to so a simple multiply:
>
> acc r0 # clear accumulator, discarding its value (r0 reads as 0,
> and sinks writes)
> mac rSRC1, rSRC2 # multiply sources, store result in accumulator
> acc rDEST # fetch accumulator value to rDEST
>
> What's the best way to model simple MUL as this 3-insn sequence in the
> LLVM backend?
>
> Should the internal accumulation register be explicitly modeled as its
> own...