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Here is an slightly updated version of the paravirt_ops patch. If your comments and criticism were welcome before, now it's even more! There are some issues that are _not_ addressed in this revision, and here are the causes: * split debugreg into multiple functions, suggested by Andi: - Me and jsfg agree that introducing more pvops (specially 14!) is not worthwhile. So, although we do

Here is an slightly updated version of the paravirt_ops patch. If your comments and criticism were welcome before, now it's even more! There are some issues that are _not_ addressed in this revision, and here are the causes: * split debugreg into multiple functions, suggested by Andi: - Me and jsfg agree that introducing more pvops (specially 14!) is not worthwhile. So, although we do

...ead_cr2(); + cr3 = read_cr3(); + cr4 = read_cr4(); printk("FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", fs,fsindex,gs,gsindex,shadowgs); @@ -578,7 +579,7 @@ __switch_to(struct task_struct *prev_p, /* * Reload esp0, LDT and the page table pointer: */ - tss->rsp0 = next->rsp0; + load_rsp0(tss, next); /* * Switch DS and ES. Index: clean-start/arch/x86_64/kernel/reboot.c =================================================================== --- clean-start.orig/arch/x86_64/kernel/reboot.c +++ clean-start/arch/x86_64/kernel/reboot.c @@ -15,6 +15,7 @@...

...ead_cr2(); + cr3 = read_cr3(); + cr4 = read_cr4(); printk("FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", fs,fsindex,gs,gsindex,shadowgs); @@ -578,7 +579,7 @@ __switch_to(struct task_struct *prev_p, /* * Reload esp0, LDT and the page table pointer: */ - tss->rsp0 = next->rsp0; + load_rsp0(tss, next); /* * Switch DS and ES. Index: clean-start/arch/x86_64/kernel/reboot.c =================================================================== --- clean-start.orig/arch/x86_64/kernel/reboot.c +++ clean-start/arch/x86_64/kernel/reboot.c @@ -15,6 +15,7 @@...

This is hopefully the last iteration of the pvops64 patch. >From the last version, we have only one change, which is include/asm-x86_64/processor.h: There were still one survivor in raw asm. Also, git screwed me up for some reason, and the 25th patch was missing the new files, paravirt.{c,h}. (although I do remember having git-add'ed it, but who knows...) Andrew, could you please push it

This is hopefully the last iteration of the pvops64 patch. >From the last version, we have only one change, which is include/asm-x86_64/processor.h: There were still one survivor in raw asm. Also, git screwed me up for some reason, and the 25th patch was missing the new files, paravirt.{c,h}. (although I do remember having git-add'ed it, but who knows...) Andrew, could you please push it

Hi folks, After some time away from it, and a big rebase as a consequence, here is the updated version of paravirt_ops for x86_64, heading to inclusion. Your criticism is of course, very welcome. Have fun -- arch/x86_64/Kconfig | 11 arch/x86_64/ia32/syscall32.c | 2 arch/x86_64/kernel/Makefile | 1 arch/x86_64/kernel/apic.c | 2

Hi folks, After some time away from it, and a big rebase as a consequence, here is the updated version of paravirt_ops for x86_64, heading to inclusion. Your criticism is of course, very welcome. Have fun -- arch/x86_64/Kconfig | 11 arch/x86_64/ia32/syscall32.c | 2 arch/x86_64/kernel/Makefile | 1 arch/x86_64/kernel/apic.c | 2

...ed() 0 #define get_debugreg(var, register) \ __asm__("movq %%db" #register ", %0" \ :"=r" (var)) @@ -306,6 +281,31 @@ struct thread_struct { __asm__("movq %0,%%db" #register \ : /* no output */ \ :"r" (value)) +#define load_rsp0(tss, thread) \ + do { (tss)->rsp0 = (thread)->rsp0; } while(0) +#endif + +/* + * Save the cr4 feature set we're using (ie + * Pentium 4MB enable and PPro Global page + * enable), so that any CPU's that boot up + * after us can get the correct flags. + */ +extern unsigned long mmu_c...

...ed() 0 #define get_debugreg(var, register) \ __asm__("movq %%db" #register ", %0" \ :"=r" (var)) @@ -306,6 +281,31 @@ struct thread_struct { __asm__("movq %0,%%db" #register \ : /* no output */ \ :"r" (value)) +#define load_rsp0(tss, thread) \ + do { (tss)->rsp0 = (thread)->rsp0; } while(0) +#endif + +/* + * Save the cr4 feature set we're using (ie + * Pentium 4MB enable and PPro Global page + * enable), so that any CPU's that boot up + * after us can get the correct flags. + */ +extern unsigned long mmu_c...

...we hold many more cr3/pgd's then the i386 version does. This is because we have the ability to implement page cleaning at a lower level, and this lets us limit the amount of pages the guest can take from the host. Interrupts: =========== When an interrupt goes off, we've put the tss->rsp0 to point to the vcpu struct regs field. This way we push onto the vcpu struct the trapnum errcord, rip, cs, rflags, rsp and ss regs. Alse we put onto this field the guests regs and cr3. This is somewhat similar to the i386 way of doing things. We then put back the host gdt, idt, tr and cr3 regs an...

...we hold many more cr3/pgd's then the i386 version does. This is because we have the ability to implement page cleaning at a lower level, and this lets us limit the amount of pages the guest can take from the host. Interrupts: =========== When an interrupt goes off, we've put the tss->rsp0 to point to the vcpu struct regs field. This way we push onto the vcpu struct the trapnum errcord, rip, cs, rflags, rsp and ss regs. Alse we put onto this field the guests regs and cr3. This is somewhat similar to the i386 way of doing things. We then put back the host gdt, idt, tr and cr3 regs an...

...ead_cr2(); + cr3 = read_cr3(); + cr4 = read_cr4(); printk("FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", fs,fsindex,gs,gsindex,shadowgs); @@ -574,7 +574,7 @@ __switch_to(struct task_struct *prev_p, /* * Reload esp0, LDT and the page table pointer: */ - tss->rsp0 = next->rsp0; + load_rsp0(tss,next); /* * Switch DS and ES. Index: linux-2.6.19-quilt/arch/x86_64/kernel/setup.c =================================================================== --- linux-2.6.19-quilt.orig/arch/x86_64/kernel/setup.c +++ linux-2.6.19-quilt/arch/x86_64/kernel/setup.c @@...

...ead_cr2(); + cr3 = read_cr3(); + cr4 = read_cr4(); printk("FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", fs,fsindex,gs,gsindex,shadowgs); @@ -574,7 +574,7 @@ __switch_to(struct task_struct *prev_p, /* * Reload esp0, LDT and the page table pointer: */ - tss->rsp0 = next->rsp0; + load_rsp0(tss,next); /* * Switch DS and ES. Index: linux-2.6.19-quilt/arch/x86_64/kernel/setup.c =================================================================== --- linux-2.6.19-quilt.orig/arch/x86_64/kernel/setup.c +++ linux-2.6.19-quilt/arch/x86_64/kernel/setup.c @@...

...:"); +extern char lguest_noirq_start[], lguest_noirq_end[]; +#endif + +extern void lguest_iret(void); +asm("lguest_iret:" + " movq $" __stringify(LHCALL_IRET) ", %rax\n" + " int $" __stringify(LGUEST_TRAP_ENTRY) ); + + +static void lguest_load_rsp0(struct tss_struct *tss, + struct thread_struct *thread) +{ + lazy_hcall(LHCALL_SET_STACK, thread->rsp0, THREAD_SIZE/PAGE_SIZE, 0); +} + +static void lguest_load_tr_desc(void) +{ +} + +static void lguest_set_ldt(const void *addr, unsigned entries) +{ + /* FIXME: Implement. */ + BUG_ON(ent...

...:"); +extern char lguest_noirq_start[], lguest_noirq_end[]; +#endif + +extern void lguest_iret(void); +asm("lguest_iret:" + " movq $" __stringify(LHCALL_IRET) ", %rax\n" + " int $" __stringify(LGUEST_TRAP_ENTRY) ); + + +static void lguest_load_rsp0(struct tss_struct *tss, + struct thread_struct *thread) +{ + lazy_hcall(LHCALL_SET_STACK, thread->rsp0, THREAD_SIZE/PAGE_SIZE, 0); +} + +static void lguest_load_tr_desc(void) +{ +} + +static void lguest_set_ldt(const void *addr, unsigned entries) +{ + /* FIXME: Implement. */ + BUG_ON(ent...

...+static void native_write_gdt_entry(void *dt, int entrynum, u32 low, u32 high) +{ + native_write_dt_entry(dt, entrynum, low, high); +} + +static void native_write_idt_entry(void *dt, int entrynum, u32 low, u32 high) +{ + native_write_dt_entry(dt, entrynum, low, high); +} + +static void native_load_rsp0(struct tss_struct *tss, + struct thread_struct *thread) +{ + tss->rsp0 = thread->rsp0; +} + +static void native_io_delay(void) +{ + asm volatile("outb %al,$0x80"); +} + +void native_pagetable_setup_start(pgd_t *base) +{ + int i; + + /* + * Init entries of the first-level p...

...+static void native_write_gdt_entry(void *dt, int entrynum, u32 low, u32 high) +{ + native_write_dt_entry(dt, entrynum, low, high); +} + +static void native_write_idt_entry(void *dt, int entrynum, u32 low, u32 high) +{ + native_write_dt_entry(dt, entrynum, low, high); +} + +static void native_load_rsp0(struct tss_struct *tss, + struct thread_struct *thread) +{ + tss->rsp0 = thread->rsp0; +} + +static void native_io_delay(void) +{ + asm volatile("outb %al,$0x80"); +} + +void native_pagetable_setup_start(pgd_t *base) +{ + int i; + + /* + * Init entries of the first-level p...

...80 curthread = 0xfffffe00264b8000: pid 12 "irq265: ix0:que 0" curpcb = 0xffffff9a3ea71bc0 fpcurthread = none idlethread = 0xfffffe00262bc470: tid 100003 "idle: cpu0" curpmap = 0xffffffff812d5af0 tssp = 0xffffffff814e0960 commontssp = 0xffffffff814e0960 rsp0 = 0xffffff9a3ea71bc0 gs32p = 0xffffffff814deab8 ldt = 0xffffffff814deaf8 tss = 0xffffffff814deae8 spin locks held: db:0:pcpu> bt Tracing pid 12 tid 100069 td 0xfffffe00264b8000 kdb_enter() at kdb_enter+0x3b panic() at panic+0x1d1 soabort() at soabort+0x99 syncac...