Displaying 5 results from an estimated 5 matches for "rs_assign".
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2018 Dec 05
2
Strange regalloc behaviour: one more available register causes much worse allocation
...into stage RS_Split
immediately. This makes the chain of evictions after %396 not happen, but
that gives us one extra spill and we still get one pair of copies in
bb.17.switchdest13.
* In RAGreedy::evictInterference put evicted registers into a new RS_Evicted
stage, which is like RS_Assign but can't evict anything. This seemed to give
OK results but was a mess and I didn't understand what I was doing, so I
threw it away.
* Turn on the ConsiderLocalIntervalCost option, as it's supposed to help with
eviction chains like this. Unfortunately it doesn't work...
2018 Dec 05
3
Strange regalloc behaviour: one more available register causes much worse allocation
...into stage RS_Split
immediately. This makes the chain of evictions after %396 not happen, but
that gives us one extra spill and we still get one pair of copies in
bb.17.switchdest13.
* In RAGreedy::evictInterference put evicted registers into a new RS_Evicted
stage, which is like RS_Assign but can't evict anything. This seemed to give
OK results but was a mess and I didn't understand what I was doing, so I
threw it away.
* Turn on the ConsiderLocalIntervalCost option, as it's supposed to help with
eviction chains like this. Unfortunately it doesn't work...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...to $r6: R6 [48r,288r:0) 0 at 48r
selectOrSplit tGPR:%3 [80r,336r:0) 0 at 80r weight:3.048780e-03 w=3.048780e-03
Checking interference for %3 [80r,336r:0) 0 at 80r weight:3.048780e-03
$r0: IK_RegMask
$r1: IK_RegMask
$r2: IK_RegMask
$r3: IK_RegMask
$r4: IK_VirtReg
$r5: IK_VirtReg
$r6: IK_VirtReg
RS_Assign Cascade 0
wait for second round
queuing new interval: %3 [80r,336r:0) 0 at 80r weight:3.048780e-03
selectOrSplit tGPR:%3 [80r,336r:0) 0 at 80r weight:3.048780e-03 w=3.048780e-03
Checking interference for %3 [80r,336r:0) 0 at 80r weight:3.048780e-03
$r0: IK_RegMask
$r1: IK_RegMask
$r2: IK_RegMas...
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...sed hint $r1
assigning %1 to $r5: R5 [32r,400r:0) 0 at 32r
selectOrSplit tGPR:%2 [16r,320r:0) 0 at 16r weight:5.738636e-03 w=5.738636e-03
hints: $r2 $r1
missed hint $r2
assigning %2 to $r6: R6 [16r,320r:0) 0 at 16r
selectOrSplit tGPR:%3 [80r,432r:0) 0 at 80r weight:3.324468e-03 w=3.324468e-03
RS_Assign Cascade 0
wait for second round
queuing new interval: %3 [80r,432r:0) 0 at 80r weight:3.324468e-03
selectOrSplit tGPR:%3 [80r,432r:0) 0 at 80r weight:3.324468e-03 w=3.324468e-03
RS_Split Cascade 0
Analyze counted 5 instrs in 1 blocks, through 0 blocks.
tryLocalSplit: 80r 144r 240r 336r 432r
4 r...