Displaying 7 results from an estimated 7 matches for "rpp_llvm".
2019 Jul 12
2
[cfe-dev] ARM float16 intrinsic test
....eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 28, 1
.eabi_attribute 38, 1
.eabi_attribute 18, 4
.eabi_attribute 26, 2
.eabi_attribute 14, 0
.file "arm.cpp"
unhandled vld/vst lane type
UNREACHABLE executed at
/home/nancy/rpp_llvm/llvm-project/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:2072!
Stack dump:
0. Program arguments:
/home/nancy/rpp_llvm/build-project/bin/clang-8 -cc1 -triple
armv8.2a-arm-unknown-eabihf -S -disable-free -main-file-name arm.cpp
-mrelocation-model static -mthread-model posix -mdisable-fp-elim
-fmath-er...
2019 Jul 12
2
[cfe-dev] ARM float16 intrinsic test
...x
half> %14, <4 x half> %15, <4 x half> %16, i32 3, i32 2)
declare void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8*, <4 x half>, <4 x
half>, <4 x half>, <4 x half>, i32, i32) #1
$$COMP_ROOT/llc arm.ll
unhandled vld/vst lane type
UNREACHABLE executed at
/home/nancy/rpp_llvm/llvm-project/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:2072!
May I know how to compile this .cpp correctly from FE to BE?
--
Best Regards,
Yu Rong Tan
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2019 Sep 27
2
Maybe a TableGen bug?
...(set i16v:$rs1, (load (add i32:$rbase, (shl (*sext
(i16 (bitconvert i16v:$roffset))*), i32:$rshift))))];
.....
i16v is a new type we added, same as i16, only name differ.
While -gen-dag-isel, hit the following issue:
Value type size is target-dependent. Ask TLI.
UNREACHABLE executed at
/home/nancy/rpp_llvm/rpp_clang/llvm/include/llvm/Support/MachineValueType.h:643!
Is that a TableGen bug?
llvm 8.0.0 version.
--
Best Regards,
Yu Rong Tan
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2019 Nov 20
4
Tablegen PAT limitation?
...nbsp; let DecoderMethod = "decodeUImmOperand<2>";
}
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffs...
2019 Nov 21
2
Tablegen PAT limitation?
...nbsp; let DecoderMethod = "decodeUImmOperand<2>";
}
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffs...
2019 Nov 22
2
Tablegen PAT limitation?
...nbsp; let DecoderMethod = "decodeUImmOperand<2>";
}
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffs...
2019 Nov 25
2
Tablegen PAT limitation?
...nbsp; let DecoderMethod = "decodeUImmOperand<2>";
}
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffs...