Displaying 5 results from an estimated 5 matches for "rp_write_config".
2018 Sep 05
1
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...s logging
> access to the emulated bridge is already sufficient. The Prefetchable
> Base Upper 32 Bits register is at offset 0x28.
>
> In a trace where the Nvidia device is disabled/enabled via Device
> Manager, I see writes on the enable path:
>
> 2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4)
Did you do anything special to get an emulated bridge included in this setup?
Folllowing the instructions at
https://wiki.archlinux.org/index.php/PCI_passthrough_via_OVMF I can
successfully pass through devices to windows running under
virt-manager. In the nvidia GP...
2018 Aug 30
2
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...s logging
> access to the emulated bridge is already sufficient. The Prefetchable
> Base Upper 32 Bits register is at offset 0x28.
>
> In a trace where the Nvidia device is disabled/enabled via Device
> Manager, I see writes on the enable path:
>
> 2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4)
>
> For Linux, I only see one write at startup, none on runtime resume.
> I did not test system sleep/resume. (disable/enable is arguably a bit
> different from system s/r, you may want to do additional testing here.)
I managed to install Win10 Home under...
2018 Aug 28
6
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
On Fri, Aug 24, 2018 at 11:42 PM, Peter Wu <peter at lekensteyn.nl> wrote:
> Are these systems also affected through runtime power management? For
> example:
>
> modprobe nouveau # should enable runtime PM
> sleep 6 # wait for runtime suspend to kick in
> lspci -s1: # runtime resume by reading PCI config space
>
> On laptops from
2018 Aug 30
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...mulated bridge is already sufficient. The Prefetchable
> > Base Upper 32 Bits register is at offset 0x28.
> >
> > In a trace where the Nvidia device is disabled/enabled via Device
> > Manager, I see writes on the enable path:
> >
> > 2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4)
> >
> > For Linux, I only see one write at startup, none on runtime resume.
> > I did not test system sleep/resume. (disable/enable is arguably a bit
> > different from system s/r, you may want to do additional testing here.)
>
> I manag...
2018 Aug 28
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...be passed to a guest, but perhaps logging
access to the emulated bridge is already sufficient. The Prefetchable
Base Upper 32 Bits register is at offset 0x28.
In a trace where the Nvidia device is disabled/enabled via Device
Manager, I see writes on the enable path:
2571 at 1535108904.593107:rp_write_config (ioh3420, @0x28, 0x0, len=0x4)
For Linux, I only see one write at startup, none on runtime resume.
I did not test system sleep/resume. (disable/enable is arguably a bit
different from system s/r, you may want to do additional testing here.)
Full log for WIndows 10 and Linux:
https://github.com/Le...