search for: rotr

Displaying 20 results from an estimated 24 matches for "rotr".

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2007 Mar 30
1
[LLVMdev] Cleanups in ROTL/ROTR DAG combiner code
The attached patch contains: - Cleanups in the DAGCombiner.cpp ROTL/ROTR combine code, primarily helping me to fix 80col violations (benefiting the code as a whole). - Detect sign/zext/any-extended versions of ROTL/ROTR patterns. - Allow custom lowering for ROTL/ROTR (needed in the CellSPU's case for 8-bit rotates, when only 16-bit and 32-bit rotates are act...
2013 Oct 03
2
[LLVMdev] Question about DAGCombiner::MatchRotate function
Hi all, While I test "clang-tests/gcc-4_2-testsuite/src/gcc.c-torture/execute/20020226-1.c", I faced something wrong with "DAGCombiner::MatchRotate" function. This function tries to consume some patterns and generate "ROTL" or "ROTR" dag node as following comments: "DAGCombier::MatchRotate" function in DAGCombiner.cpp Pattern1 // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext...
2012 Jul 29
2
[LLVMdev] rotate
in C or C++, how can I get clang/llvm to try and do a "rotate". (want to test this code in the mips16 port) i.e. emit rotr node. tia. reed
2007 Feb 24
2
SHA256 password patch
Hi, I made a patch against branch-1.0 for SHA256 password hashing support for Dovecot. Courier Authlib supports this hashing scheme and in order to migrate from Courier to Dovecot, I've added SHA256 support to Dovecot. The attached patch is based on BSD licensed code from Olivier Gay (http://www.ouah.org/ogay/sha2/). Changes made by me in Olivier's sha2{.h,.c} code: - Prototype for
2012 Jul 29
0
[LLVMdev] rotate
...pile with (assuming you are on OS X): ====== ISYSROOT=$(xcodebuild -sdk macosx -version PlatformPath)/Developer/SDKs/MacOSX10.8.sdk $(xcrun -find clang) -isysroot $ISYSROOT ror.c -c -S -Os -o - ====== yielding an assembly output of: ====== .section __TEXT,__text,regular,pure_instructions .globl _rotr _rotr: ## @rotr .cfi_startproc ## BB#0: pushq %rbp Ltmp2: .cfi_def_cfa_offset 16 Ltmp3: .cfi_offset %rbp, -16 movq %rsp, %rbp Ltmp4: .cfi_def_cfa_register %rbp movb %sil, %cl rorl %cl, %edi <==== Rotate instruction movl %edi,...
2012 Jul 29
3
[LLVMdev] rotate
...===== > ISYSROOT=$(xcodebuild -sdk macosx -version PlatformPath)/Developer/SDKs/MacOSX10.8.sdk > $(xcrun -find clang) -isysroot $ISYSROOT ror.c -c -S -Os -o - > ====== > > yielding an assembly output of: > ====== > .section __TEXT,__text,regular,pure_instructions > .globl _rotr > _rotr: ## @rotr > .cfi_startproc > ## BB#0: > pushq %rbp > Ltmp2: > .cfi_def_cfa_offset 16 > Ltmp3: > .cfi_offset %rbp, -16 > movq %rsp, %rbp > Ltmp4: > .cfi_def_cfa_register %rbp > movb %sil, %cl > rorl %cl, %edi<...
2009 Feb 03
0
[LLVMdev] rol/ror llvm instruction set
...ends do know about rotate instructions on > targets that have them, though, and the llvm optimizers are pretty > smart about recognizing the usual ways to express rotate with shift/ > and/or, as below. > Look in the DAGCombiner.cpp file to see which patterns it translates into ROTL and ROTR instructions. -bw
2009 Feb 03
2
[LLVMdev] rol/ror llvm instruction set
On Feb 3, 2009, at 2:35 PMPST, Mike Stump wrote: > On Feb 3, 2009, at 2:28 PM, Kasra wrote: >> I was looking around the LLVM instruction set and I failed to find >> ROL and ROR instructions. Is there any plans on adding these >> instructions to LLVM? > > Not sure what you mean: He's referring to the LLVM IR, I think, and it's true that doesn't have
2018 Jul 02
2
Rotates, once again
On 7/2/2018 3:16 PM, Sanjay Patel wrote: > I also agree that the per-element rotate for vectors is what we want for > this intrinsic. > > So I have this so far: > > declare i32 @llvm.catshift.i32(i32 %a, i32 %b, i32 %shift_amount) > declare <2 x i32> @llvm.catshift.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %shift_amount) > > For
2012 Jul 29
0
[LLVMdev] rotate
...ild -sdk macosx -version PlatformPath)/Developer/SDKs/MacOSX10.8.sdk >> $(xcrun -find clang) -isysroot $ISYSROOT ror.c -c -S -Os -o - >> ====== >> >> yielding an assembly output of: >> ====== >> .section __TEXT,__text,regular,pure_instructions >> .globl _rotr >> _rotr: ## @rotr >> .cfi_startproc >> ## BB#0: >> pushq %rbp >> Ltmp2: >> .cfi_def_cfa_offset 16 >> Ltmp3: >> .cfi_offset %rbp, -16 >> movq %rsp, %rbp >> Ltmp4: >> .cfi_def_cfa_register %rbp &...
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...case ISD::SREM: + case ISD::UREM: + case ISD::FADD: + case ISD::FSUB: + case ISD::FMUL: + case ISD::FDIV: + case ISD::FREM: + case ISD::AND: + case ISD::OR: + case ISD::XOR: + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: + case ISD::CTTZ: + case ISD::CTLZ: + case ISD::CTPOP: + case ISD::SELECT: + case ISD::SELECT_CC: + case ISD::SINT_TO_FP: + case ISD::UINT_TO_FP: + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: + case ISD::FNEG: + case ISD::FABS: + case ISD::FSQRT: + case ISD...
2009 Feb 03
6
[LLVMdev] rol/ror llvm instruction set
...t; > targets that have them, though, and the llvm > optimizers are pretty > > smart about recognizing the usual ways to express > rotate with shift/ > > and/or, as below. > > > Look in the DAGCombiner.cpp file to see which patterns it > translates > into ROTL and ROTR instructions. > > -bw I guess the backends could know about the instructions. But I am not convinced why it is beneficial not to have ROR and ROL instructions within llvm. > Look in the DAGCombiner.cpp file to see which patterns it > translates > into ROTL and ROTR instructions....
2001 Sep 12
0
AES update..
...500 cycles = 51.2 mbits/sec - -*/ - -#include "config.h" #include "rijndael.h" - -void gen_tabs __P((void)); - -/* 3. Basic macros for speeding up generic operations */ - -/* Circular rotate of 32 bit values */ - -#define rotr(x,n) (((x) >> ((int)(n))) | ((x) << (32 - (int)(n)))) -#define rotl(x,n) (((x) << ((int)(n))) | ((x) >> (32 - (int)(n)))) - -/* Invert byte order in a 32 bit variable */ - -#define bswap(x) ((rotl(x, 8) & 0x00ff00ff) | (rotr(x, 8) & 0...
2009 May 20
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...case ISD::SREM: + case ISD::UREM: + case ISD::FADD: + case ISD::FSUB: + case ISD::FMUL: + case ISD::FDIV: + case ISD::FREM: + case ISD::AND: + case ISD::OR: + case ISD::XOR: + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: + case ISD::CTTZ: + case ISD::CTLZ: + case ISD::CTPOP: + case ISD::SELECT: + case ISD::SELECT_CC: + case ISD::ZERO_EXTEND: + case ISD::ANY_EXTEND: + case ISD::TRUNCATE: + case ISD::SIGN_EXTEND: + case ISD::SINT_TO_FP: + case ISD::UINT_TO_FP: + case ISD::FP_TO_SI...
2012 Jul 31
1
[LLVMdev] [llvm-commits] rotate
...ther languages. It seems wasteful for an optimizer to break apart an intrinsic into its elemental pieces in order for LLVM to put them back together. This was done in our compiler for some time and it cluttered up the interface code. Just curious... what kind of optimizations are done on ISD::ROTL/ROTR? We're able to preform certain InstCombines and other peeps when we see a binary operator. I do not have any experience trying to optimize ISD::ROTL. On Tue, Jul 31, 2012 at 12:17 PM, Eli Friedman <eli.friedman at gmail.com>wrote: > On Tue, Jul 31, 2012 at 8:42 AM, Cameron McInally &...
2020 Sep 25
20
[RFC PATCH 00/19] vhost-user-rpmb (Replay Protected Memory Block)
Hi, This is an initial implementation of a vhost-user backend for the VirtIO RPMB device. The device is currently in the draft of the next VirtIO specification and describes block device which uses combination of a key, nonce, hashing and a persistent write counter to prevent replay attacks (hence Replay Protected Memory Block). It is implemented as a vhost-user device because we want to
2012 Jul 31
0
[LLVMdev] [llvm-commits] rotate
On Tue, Jul 31, 2012 at 8:42 AM, Cameron McInally <cameron.mcinally at nyu.edu> wrote: > Andy, > > Here is the left circular shift operator patch. I apologize to the reviewer > in advance. The patch has a good bit of fine detail. Any > comments/criticisms? > > Some caveats... > > 1) This is just the bare minimum needed to make the left circular shift > operator
2009 Jan 20
0
[LLVMdev] cygwin build patch
On Jan 20, 2009, at 1:22 AM, Jay Foad wrote: >>> I realise that the DataTypes.h.in part might be controversial. Also, >>> there's probably a better place to put it, but I'm not sure where. >> >> I didn't apply this part. What problems does it cause to not have >> this? Can we fix uses of max and min? > > I could try to fix this by changing
2009 Jan 20
4
[LLVMdev] cygwin build patch
>> I realise that the DataTypes.h.in part might be controversial. Also, >> there's probably a better place to put it, but I'm not sure where. > > I didn't apply this part. What problems does it cause to not have > this? Can we fix uses of max and min? I get these errors in lib: .../lib/Analysis/ValueTracking.cpp:162: error: no matching function for call to
2012 Jul 31
3
[LLVMdev] rotate
Andy, Here is the left circular shift operator patch. I apologize to the reviewer in advance. The patch has a good bit of fine detail. Any comments/criticisms? Some caveats... 1) This is just the bare minimum needed to make the left circular shift operator work (e.g. no instruction combining). 2) I tried my best to select operator names in the existing style; please feel free to change them as