search for: rmorel

On Fri, Oct 25, 2013 at 7:43 AM, Robert Morell <rmorell at nvidia.com> wrote: > On Mon, Sep 30, 2013 at 10:44:12AM -0700, Lucas Stach wrote: >> Hi, >> >> recently we tried to enable MSI interrupts with nouveau. Unfortunately >> there have been some reports of things failing with certain cards, where >> it isn't e...

...P stuff is about surface RED ops, the existing code uses it but I'm going to leave it for image support and break direct buffer accesses directly into OP_ATOM (and in NVIDIA terminology RED is just ATOM without a destination). Thanks, -ilia On Fri, Oct 2, 2015 at 5:48 PM, Robert Morell <rmorell at nvidia.com> wrote: > Hi Ilia, > > Error 0x10 is INVALID_ADDR_SPACE. It is triggered when an ATOM or RED [1] > instruction accesses local or shared memory. Global memory accesses are the > only allowed accesses for ATOM and RED instructions. > > > Note that SM30 also h...

On Thu, May 21, 2015 at 10:05 AM, Robert Morell <rmorell at nvidia.com> wrote: > Hi Ilia, > > On Sat, May 02, 2015 at 12:34:21PM -0400, Ilia Mirkin wrote: >> Hi, >> >> As I'm looking to add some support to nouveau for features like atomic >> counters and images, I'm running into some confusion about what the &...

On Fri, Oct 2, 2015 at 6:14 PM, Robert Morell <rmorell at nvidia.com> wrote: > Hi Ilia, > > On Fri, Oct 02, 2015 at 06:05:21PM -0400, Ilia Mirkin wrote: >> Hi Robert, >> >> Thanks for the quick response! That goes in line with my observations >> which is that these things happen when using an ATOM/RED instruction. &...

On Mon, Oct 26, 2015 at 03:28:59PM -0400, Ilia Mirkin wrote: > On Fri, Oct 2, 2015 at 6:14 PM, Robert Morell <rmorell at nvidia.com> wrote: > > Hi Ilia, > > > > On Fri, Oct 02, 2015 at 06:05:21PM -0400, Ilia Mirkin wrote: > >> Hi Robert, > >> > >> Thanks for the quick response! That goes in line with my observations > >> which is that these things happen wh...

On Fri, Nov 06, 2015 at 04:15:29PM -0500, Ilia Mirkin wrote: > In order for ATOM.*/RED.* to work, the addresses in question must > *NOT* be inside of the 16MB local/shared windows. So if I'm getting > that error, the address must be inside. Yes, that's my understanding. > If so, this may be a reasonable explanation for what I'm seeing -- Cool, I'm happy it helps.

On Thu, Oct 24, 2013 at 04:03:12PM -0700, Ben Skeggs wrote: > On Fri, Oct 25, 2013 at 7:43 AM, Robert Morell <rmorell at nvidia.com> wrote: > > On Mon, Sep 30, 2013 at 10:44:12AM -0700, Lucas Stach wrote: > >> Hi, > >> > >> recently we tried to enable MSI interrupts with nouveau. Unfortunately > >> there have been some reports of things failing with certain cards, wher...

On Fri, Nov 6, 2015 at 3:59 PM, Robert Morell <rmorell at nvidia.com> wrote: > On Fri, Oct 02, 2015 at 06:05:21PM -0400, Ilia Mirkin wrote: >> Could you advise what the proper way of indicating >> that the memory is "global" to the op? I'm sure I'm just missing >> something simple. If you show me what to look...

...it for image > support and break direct buffer accesses directly into OP_ATOM (and in > NVIDIA terminology RED is just ATOM without a destination). Neat. I'll take a look at it. Thanks, Robert > Thanks, > > -ilia > > On Fri, Oct 2, 2015 at 5:48 PM, Robert Morell <rmorell at nvidia.com> wrote: > > Hi Ilia, > > > > Error 0x10 is INVALID_ADDR_SPACE. It is triggered when an ATOM or RED [1] > > instruction accesses local or shared memory. Global memory accesses are the > > only allowed accesses for ATOM and RED instructions. > > &...

Hi, recently we tried to enable MSI interrupts with nouveau. Unfortunately there have been some reports of things failing with certain cards, where it isn't entirely clear if this is a GPU errata or some other component in the PCIe chain failing. Could you perhaps investigate if there are any known Nvidia GPU erratas with regard to MSI interrupts, or maybe tell us the generations of cards

On Fri, Oct 02, 2015 at 06:05:21PM -0400, Ilia Mirkin wrote: > Could you advise what the proper way of indicating > that the memory is "global" to the op? I'm sure I'm just missing > something simple. If you show me what to look for in SM35 I can > probably find it on my own for SM20/SM30/SM50. Sorry again for the delay. Here's what I've been able to find

Hi, As I'm looking to add some support to nouveau for features like atomic counters and images, I'm running into some confusion about what the first word of the shader header means. Here is the definition as we have it today: https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_shaders.xml VS/HS/DS/GS: <reg32 offset="0" name="0"> <bitfield

Hello, I've recently come across an error reported by the GPU and would like to know what it means and especially what causes it to be triggered. Any information would be very useful: I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is what we currently have in nouveau: <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched -->

...Robert Jennings <rcj@linux.vnet.ibm.com> Robert Lee <rob.lee@linaro.org> Robert Lemaire <rlemaire@suse.com> Robert Love <robert.w.love@intel.com> Robert Marklund <robert.marklund@stericsson.com> Robert Moore <robert.moore@intel.com> Robert Morell <rmorell@nvidia.com> Robert Nelson <robertcnelson@gmail.com> Robert Obermeier <obbi89@googlemail.com> Robert P. J. Day <rpjday@crashcourse.ca> Robert Richter <robert.richter@amd.com> Robert Richter <rric@kernel.org> Robert Schwebel <r.schwebel@pengutronix.de&...

...Robert Jennings <rcj@linux.vnet.ibm.com> Robert Lee <rob.lee@linaro.org> Robert Lemaire <rlemaire@suse.com> Robert Love <robert.w.love@intel.com> Robert Marklund <robert.marklund@stericsson.com> Robert Moore <robert.moore@intel.com> Robert Morell <rmorell@nvidia.com> Robert Nelson <robertcnelson@gmail.com> Robert Obermeier <obbi89@googlemail.com> Robert P. J. Day <rpjday@crashcourse.ca> Robert Richter <robert.richter@amd.com> Robert Richter <rric@kernel.org> Robert Schwebel <r.schwebel@pengutronix.de&...

...Robert Jennings <rcj@linux.vnet.ibm.com> Robert Lee <rob.lee@linaro.org> Robert Lemaire <rlemaire@suse.com> Robert Love <robert.w.love@intel.com> Robert Marklund <robert.marklund@stericsson.com> Robert Moore <robert.moore@intel.com> Robert Morell <rmorell@nvidia.com> Robert Nelson <robertcnelson@gmail.com> Robert Obermeier <obbi89@googlemail.com> Robert P. J. Day <rpjday@crashcourse.ca> Robert Richter <robert.richter@amd.com> Robert Richter <rric@kernel.org> Robert Schwebel <r.schwebel@pengutronix.de&...

...Robert Jennings <rcj@linux.vnet.ibm.com> Robert Lee <rob.lee@linaro.org> Robert Lemaire <rlemaire@suse.com> Robert Love <robert.w.love@intel.com> Robert Marklund <robert.marklund@stericsson.com> Robert Moore <robert.moore@intel.com> Robert Morell <rmorell@nvidia.com> Robert Nelson <robertcnelson@gmail.com> Robert Obermeier <obbi89@googlemail.com> Robert P. J. Day <rpjday@crashcourse.ca> Robert Richter <robert.richter@amd.com> Robert Richter <robert.richter@calxeda.com> Robert Richter <rric@kernel.org&...

...Robert Jennings <rcj@linux.vnet.ibm.com> Robert Lee <rob.lee@linaro.org> Robert Lemaire <rlemaire@suse.com> Robert Love <robert.w.love@intel.com> Robert Marklund <robert.marklund@stericsson.com> Robert Moore <robert.moore@intel.com> Robert Morell <rmorell@nvidia.com> Robert Nelson <robertcnelson@gmail.com> Robert Obermeier <obbi89@googlemail.com> Robert P. J. Day <rpjday@crashcourse.ca> Robert Richter <robert.richter@amd.com> Robert Richter <robert.richter@calxeda.com> Robert Richter <rric@kernel.org&...

...t; Robert Knight <knight@princeton.edu> Robert Lee <rob.lee@linaro.org> Robert Lemaire <rlemaire@suse.com> Robert Love <robert.w.love@intel.com> Robert Marklund <robert.marklund@stericsson.com> Robert Moore <robert.moore@intel.com> Robert Morell <rmorell@nvidia.com> Robert Nelson <robertcnelson@gmail.com> Robert Obermeier <obbi89@googlemail.com> Robert P. J. Day <rpjday@crashcourse.ca> Robert Richter <robert.richter@amd.com> Robert Richter <robert.richter@calxeda.com> Robert Richter <rric@kernel.org&...

...t; Robert Knight <knight@princeton.edu> Robert Lee <rob.lee@linaro.org> Robert Lemaire <rlemaire@suse.com> Robert Love <robert.w.love@intel.com> Robert Marklund <robert.marklund@stericsson.com> Robert Moore <robert.moore@intel.com> Robert Morell <rmorell@nvidia.com> Robert Nelson <robertcnelson@gmail.com> Robert Obermeier <obbi89@googlemail.com> Robert P. J. Day <rpjday@crashcourse.ca> Robert Richter <robert.richter@amd.com> Robert Richter <robert.richter@calxeda.com> Robert Richter <rric@kernel.org&...