Displaying 6 results from an estimated 6 matches for "rldicl".
2016 Sep 07
2
[PowerPC] Recent branch too far breakage
...messages:
/tmp/PPCInstPrinter-84c835.s:7671: Error: operand out of range
(0x0000000000008004 is not between 0xffffffffffff8000 and
0x0000000000007ffc)
The offending line is the bne branch in this snippet:
.LBB24_787:
ld 3, 16(29)
ld 4, 24(29)
sub 4, 4, 3
rldicl 4, 4, 60, 4
cmplwi 0, 4, 3
bne 0, .LBB24_2630
Could this be because of a recent change in the PowerPC code generator
or just because PPCInstPrinter.cpp changed a bit and exposed a
pre-existing bug?
-Rich
2016 Sep 07
2
[PowerPC] Recent branch too far breakage
...8004 is not between 0xffffffffffff8000 and
> > 0x0000000000007ffc)
> >
> > The offending line is the bne branch in this snippet:
> >
> > .LBB24_787:
> > ld 3, 16(29)
> > ld 4, 24(29)
> > sub 4, 4, 3
> > rldicl 4, 4, 60, 4
> > cmplwi 0, 4, 3
> > bne 0, .LBB24_2630
> >
> > Could this be because of a recent change in the PowerPC code
> > generator
> > or just because PPCInstPrinter.cpp changed a bit and exposed a
> > pre-existing bug?
> &g...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...LLVM BB %entry
Live Ins: %X3
%vreg2<def> = COPY %X3<kill>; G8RC:%vreg2
%vreg4<def> = LI 2048; GPRC:%vreg4
%vreg3<def> = OR8To4 %vreg2<kill>, %vreg2; GPRC:%vreg3 G8RC:%vreg2
%vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4
%vreg10<def> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9
%vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10
Successors according to CFG: BB#1
112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
Predecessors according to CFG: BB#0 BB#1
%vreg12<def...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %vreg13<def> = BDNZ8 %vreg13,
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...Successors according to CFG: BB#8 BB#10
the preheader is:
240B BB#3:
Predecessors according to CFG: BB#2
256B %vreg28<def> = LI 0; GPRC:%vreg28
272B %vreg30<def> = COPY %vreg17<kill>; GPRC:%vreg30,%vreg17
288B %vreg31<def> = RLDICL %vreg30<kill>, 0, 32;GPRC:%vreg31,%vreg30
304B MTCTR8 %vreg31<kill>,%CTR8<imp-def,dead>; GPRC:%vreg31
320B B <BB#8>
Successors according to CFG: BB#8
So maybe LiveInterval would need to be updated to support terminators
that define register...
2014 Jan 05
4
[LLVMdev] A question about everyone's favorite constructs: NSW and NUW
So, I know there are a lot of mixed feelings about NSW and NUW, but I'm
running into a common pattern where they really help:
void f(char *array, int i) {
// do some stuff...
g(array[i++]);
// do some more stuff...
g(array[i++]);
// more of the same
}
So, this kind of code comes up pretty frequently. Unrolled loops with an
int IV[1], encoding, decoding, compression, etc. What